From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8E442E8DE3 for ; Wed, 18 Feb 2026 21:33:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771450438; cv=none; b=GXbtsmPfPJQWF8UpRTXbu55d9CC4UZV5+GBiVo3+h9wrUiMhjg2XiZueLjHPFeqHoPCwf+kdd8AgI9YkT9kO5BenAdxMx+rKt4jpLwJpjan1f8ovBV/lK3M1LXPTMrr1mCLvsvc0GEpW9eoRmFaq8EZIWCsq+8Oz/oc0m7zxi6c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771450438; c=relaxed/simple; bh=tJ07+KZ0aRQjM9WiVUXHE0oB/eltrrSnHBhc3cT4P4M=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=glrk7Ay+YT4PSoENQ1XTF6vZm5bWe9C1cS8ant+3upYEWYF7KMqTj/LFy0/RexVTC5DG/pTdmIRY3EqtfafjlU69L590uhxUgQN3OBqFBgpL4Af8ZSVIHY3KiEJll4OqZ97sjb3LWEoOQhlVGXjKx6hkODAYeSoCiqIMRG3layE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cLjJryff; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cLjJryff" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1771450437; x=1802986437; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=tJ07+KZ0aRQjM9WiVUXHE0oB/eltrrSnHBhc3cT4P4M=; b=cLjJryffjQcF1WF9l0O8LlmQh5u6s+fC29uDXKB/oiN0i15FBHRzlmyM eemrTRDIRw/FugWrb/7xFUuEhhSKxCnNtFmRsngMXA6gh6zC5c1oimo+W HiznDzcc++FjanCxu1Gj03+i0+DEJuQlQrXzbj16h4kIqsiAts6zNwV8N /Vv17ZJb8BCfnrHPyVpA29DIR8URARpmBfdJT0guAY7Vn92HQTucQwImi ZKedUD07kKG0pDy81pWNM4VWCAidnaHh5wtIE3UYq5E82pQBpTv7xRHYQ ucbOSa8xvBuklvCWkTbosDB96qeKSb1Ff7rg6oFDPodys9mw3MvcAVQh9 A==; X-CSE-ConnectionGUID: 1Sy/9VOETwegpWWrRKYQcQ== X-CSE-MsgGUID: /Z9fGeeiSj22wWb5qCBLMg== X-IronPort-AV: E=McAfee;i="6800,10657,11705"; a="72712818" X-IronPort-AV: E=Sophos;i="6.21,299,1763452800"; d="scan'208";a="72712818" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 13:33:56 -0800 X-CSE-ConnectionGUID: JP9JNFrAT268KZFAYigvRQ== X-CSE-MsgGUID: J8YEa/XlQ5iG+TXSUmr1iA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,299,1763452800"; d="scan'208";a="214170608" Received: from unknown (HELO [10.241.243.83]) ([10.241.243.83]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2026 13:33:55 -0800 Message-ID: <1160e26b82b28c2fd20def53b9278bfc7b903e24.camel@linux.intel.com> Subject: Re: [PATCH v3 04/21] sched/cache: Make LLC id continuous From: Tim Chen To: K Prateek Nayak , "Chen, Yu C" Cc: Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org, Peter Zijlstra , "Gautham R . Shenoy" , Vincent Guittot , Ingo Molnar Date: Wed, 18 Feb 2026 13:33:55 -0800 In-Reply-To: <579c9039-cd66-41c3-8a72-e73d6f836ee8@amd.com> References: <60a05a3f50d14a7bf3b968f62cca87893c5c552c.1770760558.git.tim.c.chen@linux.intel.com> <79755f7d-cc68-4189-b6d8-850378e54017@amd.com> <95923e36-4117-4209-97aa-a92b60f2bd49@intel.com> <6a73ac0d-1fc9-49a7-87a2-65951ab2c844@amd.com> <8df218ecf39015830856c7b1053a0f777cc1ea42.camel@linux.intel.com> <579c9039-cd66-41c3-8a72-e73d6f836ee8@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-02-18 at 08:58 +0530, K Prateek Nayak wrote: > Hello Tim, >=20 > On 2/18/2026 4:42 AM, Tim Chen wrote: > > On Tue, 2026-02-17 at 13:39 +0530, K Prateek Nayak wrote: > > > Hello Chenyu, > > >=20 > > >=20 > >=20 > > [...snip...] > >=20 > >=20 > > > > > > =C2=A0=C2=A0 */ > > > > > > =C2=A0 DEFINE_PER_CPU(struct sched_domain __rcu *, sd_llc); > > > > > > =C2=A0 DEFINE_PER_CPU(int, sd_llc_size); > > > > > > -DEFINE_PER_CPU(int, sd_llc_id); > > > > > > +DEFINE_PER_CPU(int, sd_llc_id) =3D -1; > > > > > > =C2=A0 DEFINE_PER_CPU(int, sd_share_id); > > > > > > =C2=A0 DEFINE_PER_CPU(struct sched_domain_shared __rcu *, sd_ll= c_shared); > > > > > > =C2=A0 DEFINE_PER_CPU(struct sched_domain __rcu *, sd_numa); > > > > > > @@ -684,7 +685,6 @@ static void update_top_cache_domain(int cpu= ) > > > > > > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rcu_assign_pointer(per_cp= u(sd_llc, cpu), sd); > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 per_cpu(sd_llc_size, cpu) =3D si= ze; > > > > > > -=C2=A0=C2=A0=C2=A0 per_cpu(sd_llc_id, cpu) =3D id; > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rcu_assign_pointer(per_cpu(sd_ll= c_shared, cpu), sds); > > > > > > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 sd =3D lowest_flag_domain= (cpu, SD_CLUSTER); > > > > > > @@ -2567,10 +2567,18 @@ build_sched_domains(const struct cpumas= k *cpu_map, struct sched_domain_attr *att > > > > > > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Set up domains for CPU= s specified by the cpu_map: */ > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for_each_cpu(i, cpu_map) { > > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct sched_domain= _topology_level *tl; > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct sched_domain= _topology_level *tl, *tl_llc =3D NULL; > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int lid; > > > > > > =C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 s= d =3D NULL; > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for_each= _sd_topology(tl) { > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 int flags =3D 0; > > > > > > + > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 if (tl->sd_flags) > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 flags =3D (*tl->sd_flags)(); > > > > > > + > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 if (flags & SD_SHARE_LLC) > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tl_llc =3D tl; > > > > >=20 > > > > > nit. This loop breaks out when sched_domain_span(sd) covers the e= ntire > > > > > cpu_map and it might have not reached the topmost SD_SHARE_LLC do= main > > > > > yet. Is that cause for any concern? > > > > >=20 > > > >=20 > > > > Could you please elaborate a little more on this? If it covers the > > > > entire cpu_map shouldn't it stop going up to its parent domain? > > > > Do you mean, sd_llc_1 and its parent sd_llc_2 could cover the same = cpu_map, > > > > and we should let tl_llc to assigned to sd_llc_2 (sd_llc_1 be degen= erated? ) > > >=20 > > > I'm not sure if this is technically possible but assume following > > > topology: > > >=20 > > > [ LLC: 8-15 ] > > > [ SMT: 8,9 ][ SMT: 10,11 ] ... [ SMT: 14,15 ] > > >=20 > > > and the following series of events: > > >=20 > > > o All CPUs in LLC are offline to begin with (maxcpus =3D 1 like scena= rio). > > >=20 > > > o CPUs 10-15 are onlined first. > > >=20 > > > o CPU8 is put in a separate root partition and brought online. > > > (XXX: I'm not 100% sure if this is possible in this order) > > >=20 > > > o build_sched_domains() will bail out at SMT domain since the cpumap > > > is covered by tl->mask() and tl_llc =3D tl_smt. > > >=20 > > > o llc_id calculation uses the tl_smt->mask() which will not contain > > > CPUs 10-15 and CPU8 will get a unique LLC id even though there are > > > other online CPUs in the LLC with a different llc_id (!!!) > > >=20 > > >=20 > > > Instead, if we traversed to tl_mc, we would have seen all the online > > > CPUs in the MC and reused the llc_id from them. Might not be an issue= on > > > its own but if this root partition is removed later, CPU8 will contin= ue > > > to have the unique llc_id even after merging into the same MC domain. > >=20 > > There is really no reason to reuse the llc_id as far as cache aware sch= eduling > > goes in its v3 revision (see my reply to Madadi on this patch). =C2=A0 >=20 > Even I don't mind having some holes in the llc_id space when CPUs are > offlined but my major concern would be seeing an inconsistent state > where CPUs in same MC domains end up with different llc_id when after > a bunch of hotplug activity. >=20 > > =20 > > I am thinking that if we just simply rebuild LLC id across sched domain > > rebuilds, that is probably the cleanest solution. There could be some r= aces > > in cpus_share_cache() as llc_id gets reassigned for some CPUs when they > > come online/offline. But we also having similar races in current mainl= ine code. > > Worst it can do is some temporary sub-optimal scheduling task placement= .=20 > >=20 > > Thoughts? >=20 > If you are suggesting populating the sd_llc_id for all the CPUs on > topology rebuild, I'm not entirely against the idea. >=20 > On a separate note, if we add a dependency on SCHED_MC for SCHED_CACHE, > we can simply look at cpu_coregroup_mask() and either allocate a new > llc_id / borrow llc id in sched_cpu_activate() when CPU is onlined or > reassign them in sched_cpu_deactivate() if an entire LLC is offlined. I also think that cpu_coregroup_mask() is a better choice than tl->mask for getting the mask of CPUs in LLC. Okay, we'll consider an implemenation along your suggestion of __sched_domains_alloc_llc_id() to reuse llc id when all CPUs in LLC deactivate. That will minimize holes in LLC ids while avoiding races in cpus_share_cache(). Thanks. Tim =20