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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-67cd91a4708sm2004919a12.14.2026.05.07.03.34.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 07 May 2026 03:34:52 -0700 (PDT) Message-ID: <1163a026-03b2-4860-a422-eb276920b4aa@oss.qualcomm.com> Date: Thu, 7 May 2026 12:34:50 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] usb: dwc3: Notify XHCI core of tunneled status To: Thinh Nguyen , Konrad Dybcio Cc: Greg Kroah-Hartman , Mathias Nyman , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "usb4-upstream@oss.qualcomm.com" , Raghavendra Thoorpu , Mika Westerberg References: <20260505-topic-dwc3_tunneling_state-v1-0-4aaa6c3c14cb@oss.qualcomm.com> <20260505-topic-dwc3_tunneling_state-v1-2-4aaa6c3c14cb@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Wv4b99fv c=1 sm=1 tr=0 ts=69fc6acf cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=ORxTflC89JRLnpgA4MQA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: HWrUA8dV0BmdywCwAmIlDjIX5i5rSRgk X-Proofpoint-GUID: HWrUA8dV0BmdywCwAmIlDjIX5i5rSRgk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDEwNCBTYWx0ZWRfX4HFqqYos+d7y WP7+xMKGOT+38d7klldNehVX1enGOhWjRYpL1in59Cf6mal2XMh4XULA76ECvi48YFtv8hnUytH uGdmS/w9jSNwoWFrfL/uB6aav8ewezkIcoZ7uY4xpQUQnY1sw/6tivY+ehvsSF6gT85dWEzI0C/ s7oMB4cqB4evdqPGTOr/hd1jILieUjdMA2yxu6m6QLisX74y+61d7xTT0Y7iI/YlJ9u9hssFIZ1 vqy4VmOVZXn7LCZ0KICNmNxhtX7Pf9+dG46E/n78ZnP/sQEt1A7jLYMywLPBeztK4+vO6trS9TN /CBm2TViEaRNeaR7YnFuSRY6OmveiKqW/L2DKA8Tj2wK+nPcQUmepdy1BloLxcDPViQE9ebx4dN Bqw7Dd0p2gMRQyxbjtb86YqkNy38jm4yaG8sAsOfI/9OBcVYSIvY/JgSK8BhsrGeaWniBl5Tv9Z l20hvwmyazW0/CnMuuA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070104 On 5/7/26 1:40 AM, Thinh Nguyen wrote: > On Tue, May 05, 2026, Konrad Dybcio wrote: >> From: Konrad Dybcio >> >> The Thunderbolt framework relies on the USB core to create device links >> for tunneled ports, so that the USB3 controller is only kept >> runtime-resumed for the duration of the tunneling. This depends on >> first knowing whether a connection is tunneled or native. >> >> Add the logic to handle that for DWC3 controllers. >> >> Signed-off-by: Konrad Dybcio >> --- >> drivers/usb/dwc3/core.c | 12 ++++++++++++ >> drivers/usb/dwc3/core.h | 18 ++++++++++++++++++ >> drivers/usb/dwc3/host.c | 12 ++++++++++++ >> 3 files changed, 42 insertions(+) >> >> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c >> index 65213896de99..7cec4911e278 100644 >> --- a/drivers/usb/dwc3/core.c >> +++ b/drivers/usb/dwc3/core.c >> @@ -162,6 +162,18 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) >> } >> EXPORT_SYMBOL_GPL(dwc3_set_prtcap); >> >> +enum usb_link_tunnel_mode dwc3_link_tunnel_mode(struct dwc3 *dwc, u8 port) >> +{ >> + /* Prior versions had no CIO support */ >> + if (!DWC3_VER_IS_WITHIN(DWC31, 191A, ANY)) >> + return USB_LINK_NATIVE; >> + >> + if (dwc3_readl(dwc, DWC3_CIOCTRL(port)) & DWC3_CIOCTRL_CIO_EN) > > The CIO register block only exists if DWC1_USB31_EN_CIO is set (and > DWC_USB31_EN_USB2_ONLY is not set). In most cases, this register block > will be reserved, register read of reserved block should be 0. But we > can't guarantee that it will always be the case. That's inconvenient because.. [...] > We shouldn't need to be doing this. This should be checked from the > xHCI driver. Check xHCI spec for PORTSC.TM and USB3 tunneling support > capability (section 7.11). ..I'm seeing only caps 0/1/2 (and 10 on some but not all) advertised (I ran a for-loop checking offsets 0..=255) How should we proceed? Konrad