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XaIAHy5tk4cq61QaeinAieCT4RwCzdxQcHjIKPlMNzWAwl+kkBroFvYuAv4AZlY8KR6Mc3QqV+z9g7JyjGQv0g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9468 On Friday, March 6, 2026 12:50=E2=80=AFAM Svyatoslav Ryhel wrote: > =D1=87=D1=82, 5 =D0=B1=D0=B5=D1=80. 2026=E2=80=AF=D1=80. =D0=BE 17:21 Svy= atoslav Ryhel =D0=BF=D0=B8=D1=88=D0=B5: > > =D0=BD=D0=B4, 25 =D1=81=D1=96=D1=87. 2026=E2=80=AF=D1=80. =D0=BE 15:13 = Svyatoslav Ryhel =D0=BF=D0=B8=D1=88=D0=B5: > > > Tegra20 and Tegra30 are fully compatible with existing Tegra DSI driv= er > > > apart from clock configuration and pad calibration which are addresse= d > > > by > > > this patch. > > >=20 > > > Signed-off-by: Svyatoslav Ryhel > > > --- > > >=20 > > > drivers/gpu/drm/tegra/drm.c | 2 + > > > drivers/gpu/drm/tegra/dsi.c | 107 +++++++++++++++++++++++++---------= -- > > > drivers/gpu/drm/tegra/dsi.h | 10 ++++ > > > 3 files changed, 88 insertions(+), 31 deletions(-) > > >=20 > > > diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.= c > > > index 4596073fe28f..5d64cd57e764 100644 > > > --- a/drivers/gpu/drm/tegra/drm.c > > > +++ b/drivers/gpu/drm/tegra/drm.c > > > @@ -1359,10 +1359,12 @@ static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, > > > host1x_drm_suspend,> >=20 > > > static const struct of_device_id host1x_drm_subdevs[] =3D { > > > =20 > > > { .compatible =3D "nvidia,tegra20-dc", }, > > >=20 > > > + { .compatible =3D "nvidia,tegra20-dsi", }, > > >=20 > > > { .compatible =3D "nvidia,tegra20-hdmi", }, > > > { .compatible =3D "nvidia,tegra20-gr2d", }, > > > { .compatible =3D "nvidia,tegra20-gr3d", }, > > > { .compatible =3D "nvidia,tegra30-dc", }, > > >=20 > > > + { .compatible =3D "nvidia,tegra30-dsi", }, > > >=20 > > > { .compatible =3D "nvidia,tegra30-hdmi", }, > > > { .compatible =3D "nvidia,tegra30-gr2d", }, > > > { .compatible =3D "nvidia,tegra30-gr3d", }, > > >=20 > > > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.= c > > > index 02a661d86751..ebc78dceaee6 100644 > > > --- a/drivers/gpu/drm/tegra/dsi.c > > > +++ b/drivers/gpu/drm/tegra/dsi.c > > > @@ -53,6 +53,11 @@ to_dsi_state(struct drm_connector_state *state) > > >=20 > > > return container_of(state, struct tegra_dsi_state, base); > > > =20 > > > } > > >=20 > > > +struct tegra_dsi_config { > > > + bool has_multiple_pad_controls; > > > + bool has_mux_parent_clk; > > > +}; > > > + > > >=20 > > > struct tegra_dsi { > > > =20 > > > struct host1x_client client; > > > struct tegra_output output; > > >=20 > > > @@ -82,6 +87,8 @@ struct tegra_dsi { > > >=20 > > > /* for ganged-mode support */ > > > struct tegra_dsi *master; > > > struct tegra_dsi *slave; > > >=20 > > > + > > > + const struct tegra_dsi_config *config; > > >=20 > > > }; > > > =20 > > > static inline struct tegra_dsi * > > >=20 > > > @@ -663,39 +670,46 @@ static int tegra_dsi_pad_enable(struct tegra_ds= i > > > *dsi)> >=20 > > > { > > > =20 > > > u32 value; > > >=20 > > > - value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | > > > DSI_PAD_CONTROL_VS1_PDIO(0); - tegra_dsi_writel(dsi, value, > > > DSI_PAD_CONTROL_0); > > > + if (dsi->config->has_multiple_pad_controls) { > > > + /* > > > + * XXX Is this still needed? The module reset is > > > deasserted right + * before this function is called. > > > + */ > > > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); > > > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); > > > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); > > > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); > > > + tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); > > > + > > > + value =3D DSI_PAD_CONTROL_VS1_PULLDN(0) | > > > DSI_PAD_CONTROL_VS1_PDIO(0); + tegra_dsi_writel(dsi, > > > value, DSI_PAD_CONTROL_0); > > > + > > > + value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7)= | > > > + DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | > > > + DSI_PAD_OUT_CLK(0x0); > > > + tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); > > > + > > > + value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | > > > DSI_PAD_PREEMP_PU_CLK(0x3) | + =20 > > > DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); + =20 > > > tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); > > > + } else { > > > + value =3D DSI_PAD_CONTROL_LPUPADJ(0x1) | > > > DSI_PAD_CONTROL_LPDNADJ(0x1) | + =20 > > > DSI_PAD_CONTROL_PREEMP_EN(0x1) | DSI_PAD_CONTROL_SLEWDNADJ(0x6) | + = =20 > > > DSI_PAD_CONTROL_SLEWUPADJ(0x6) | > > > DSI_PAD_CONTROL_PDIO(0) | + =20 > > > DSI_PAD_CONTROL_PDIO_CLK(0) | DSI_PAD_CONTROL_PULLDN_ENAB(0); + = =20 > > > tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); > > > + } > > >=20 > > > return 0; > > > =20 > > > } > > > =20 > > > static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) > > > { > > >=20 > > > - u32 value; > > >=20 > > > int err; > > >=20 > > > - /* > > > - * XXX Is this still needed? The module reset is deasserted > > > right > > > - * before this function is called. > > > - */ > > > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); > > > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); > > > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); > > > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); > > > - tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); > > > - > > >=20 > > > /* start calibration */ > > > tegra_dsi_pad_enable(dsi); > > >=20 > > > - value =3D DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | > > > - DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | > > > - DSI_PAD_OUT_CLK(0x0); > > > - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); > > > - > > > - value =3D DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(= 0x3) > > > | > > > - DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); > > > - tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); > > > - > > >=20 > > > err =3D tegra_mipi_start_calibration(dsi->mipi); > > > if (err < 0) > > > =20 > > > return err; > > >=20 > > > @@ -1568,6 +1582,7 @@ static int tegra_dsi_probe(struct platform_devi= ce > > > *pdev)> >=20 > > > if (!dsi) > > > =20 > > > return -ENOMEM; > > >=20 > > > + dsi->config =3D of_device_get_match_data(&pdev->dev); > > >=20 > > > dsi->output.dev =3D dsi->dev =3D &pdev->dev; > > > dsi->video_fifo_depth =3D 1920; > > > dsi->host_fifo_depth =3D 64; > > >=20 > > > @@ -1606,7 +1621,7 @@ static int tegra_dsi_probe(struct platform_devi= ce > > > *pdev)> >=20 > > > goto remove; > > > =20 > > > } > > >=20 > > > - dsi->clk_lp =3D devm_clk_get(&pdev->dev, "lp"); > > > + dsi->clk_lp =3D devm_clk_get_optional(&pdev->dev, "lp"); > > >=20 > > > if (IS_ERR(dsi->clk_lp)) { > > > =20 > > > err =3D dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp= ), > > > =20 > > > "cannot get low-power clock\n"); > > >=20 > > > @@ -1627,10 +1642,12 @@ static int tegra_dsi_probe(struct > > > platform_device *pdev)> >=20 > > > goto remove; > > > =20 > > > } > > >=20 > > > - err =3D tegra_dsi_setup_clocks(dsi); > > > - if (err < 0) { > > > - dev_err(&pdev->dev, "cannot setup clocks\n"); > > > - goto remove; > > > + if (dsi->config->has_mux_parent_clk) { > > > + err =3D tegra_dsi_setup_clocks(dsi); > > > + if (err < 0) { > > > + dev_err(&pdev->dev, "cannot setup clocks\n"); > > > + goto remove; > > > + } > > >=20 > > > } > > > =20 > > > dsi->regs =3D devm_platform_ioremap_resource(pdev, 0); > > >=20 > > > @@ -1694,11 +1711,39 @@ static void tegra_dsi_remove(struct > > > platform_device *pdev)> >=20 > > > tegra_mipi_free(dsi->mipi); > > > =20 > > > } > > >=20 > > > +static const struct tegra_dsi_config tegra20_dsi_config =3D { > > > + .has_multiple_pad_controls =3D false, > > > + .has_mux_parent_clk =3D false, > > > +}; > > > + > > > +/* > > > + * Tegra30 allows DSIA/DSIB to be muxed to either PLL_D or PLL_D2; t= his > > > is > > > + * simply not modeled in the clock driver yet. If this functionality= is > > > + * required, the has_mux_parent_clk flag can be set to true once the > > > clock > > > + * driver is patched. > > > + */ > > > +static const struct tegra_dsi_config tegra30_dsi_config =3D { > > > + .has_multiple_pad_controls =3D false, > > > + .has_mux_parent_clk =3D false, > > > +}; > > > + > > > +static const struct tegra_dsi_config tegra114_dsi_config =3D { > > > + .has_multiple_pad_controls =3D true, > > > + .has_mux_parent_clk =3D true, > > > +}; > > > + > > > +static const struct tegra_dsi_config tegra124_dsi_config =3D { > > > + .has_multiple_pad_controls =3D true, > > > + .has_mux_parent_clk =3D false, > > > +}; > >=20 > > Mikko, I have an update regarding Tegra124 config. If > > tegra_dsi_setup_clocks is not called for Tegra124 (has_mux_parent_clk > > =3D false) DSI will not work. I cannot say for sure what is going on > > with clocks since my tegra124 device has broken usb in mainline Linux > > and without panel is no go. I would like to address this before this > > series is picked. >=20 > Ok, from what I can tell, tegra_dsi_setup_clocks ensures that the > Tegra124 DSI parent gate clock is properly configured. I propose > setting has_mux_parent_clk to true for Tegra124, and I will add a > comment to explain why. >=20 > Smth like this: "Tegra124 and Tegra210 don't have an actual mux parent > for DSI clocks, but the gate parent clock they use requires the same > setup." Have you found something that tegra_dsi_setup_clocks is doing that could=20 affect it, or is it just because it doesn't work without? I looked at the code for clk_get_parent and clk_set_parent, and there=20 shouldn't be any effect if the requested parent was already the parent. I don't have a Tegra124 board available to me right now, but if we can't=20 figure out why this is necessary, I'd put a /* TODO: figure out why this is= =20 necessary on Tegra124 */ in the code. Perhaps you could check (with the clk_set_parent in place so you can boot)= =20 what the parent is according to the clock framework before we call=20 clk_set_parent. Mikko >=20 > Or flag name can be changed to has_mux_gate_parent_clk or any other > name which fits. >=20 > > > + > > >=20 > > > static const struct of_device_id tegra_dsi_of_match[] =3D { > > >=20 > > > - { .compatible =3D "nvidia,tegra210-dsi", }, > > > - { .compatible =3D "nvidia,tegra132-dsi", }, > > > - { .compatible =3D "nvidia,tegra124-dsi", }, > > > - { .compatible =3D "nvidia,tegra114-dsi", }, > > > + { .compatible =3D "nvidia,tegra210-dsi", .data =3D > > > &tegra124_dsi_config }, + { .compatible =3D "nvidia,tegra132-ds= i", > > > .data =3D &tegra124_dsi_config }, + { .compatible =3D > > > "nvidia,tegra124-dsi", .data =3D &tegra124_dsi_config }, + { > > > .compatible =3D "nvidia,tegra114-dsi", .data =3D &tegra114_dsi_config= }, +=20 > > > { .compatible =3D "nvidia,tegra30-dsi", .data =3D &tegra30_dsi_c= onfig > > > }, + { .compatible =3D "nvidia,tegra20-dsi", .data =3D > > > &tegra20_dsi_config },> >=20 > > > { }, > > > =20 > > > }; > > > MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); > > >=20 > > > diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.= h > > > index f39594e65e97..d834ac0c47ab 100644 > > > --- a/drivers/gpu/drm/tegra/dsi.h > > > +++ b/drivers/gpu/drm/tegra/dsi.h > > > @@ -95,6 +95,16 @@ > > >=20 > > > #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) > > > #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) > > > #define DSI_PAD_CONTROL_0 0x4b > > >=20 > > > +/* Tegra20/Tegra30 */ > > > +#define DSI_PAD_CONTROL_PULLDN_ENAB(x) (((x) & 0x1) << 28) > > > +#define DSI_PAD_CONTROL_SLEWUPADJ(x) (((x) & 0x7) << 24) > > > +#define DSI_PAD_CONTROL_SLEWDNADJ(x) (((x) & 0x7) << 20) > > > +#define DSI_PAD_CONTROL_PREEMP_EN(x) (((x) & 0x1) << 19) > > > +#define DSI_PAD_CONTROL_PDIO_CLK(x) (((x) & 0x1) << 18) > > > +#define DSI_PAD_CONTROL_PDIO(x) (((x) & 0x3) << 16) > > > +#define DSI_PAD_CONTROL_LPUPADJ(x) (((x) & 0x3) << 14) > > > +#define DSI_PAD_CONTROL_LPDNADJ(x) (((x) & 0x3) << 12) > > > +/* Tegra114+ */ > > >=20 > > > #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) > > > #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) > > > #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) > > >=20 > > > -- > > > 2.51.0