From: Daniel Walker <dwalker@mvista.com>
To: Kevin Hilman <khilman@mvista.com>
Cc: Russell King <rmk+lkml@arm.linux.org.uk>,
Ingo Molnar <mingo@elte.hu>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH -rt] ARM TLB flush fix: don't forget to re-enable preemption
Date: Wed, 23 May 2007 09:30:03 -0700 [thread overview]
Message-ID: <1179937803.15427.250.camel@imap.mvista.com> (raw)
In-Reply-To: <1179936837.7051.11.camel@vence.hilman.org>
On Wed, 2007-05-23 at 09:13 -0700, Kevin Hilman wrote:
> Note that my patch simply adds an enable to match the disable added by
> the -rt patch. I'm not sure where the disable originally came from, but
> there are disable/enable pairs scattered throughout tlbflush.h in the
> -rt patch.
>
> If this one isn't necessary, then the others probably are not either.
> In most cases there are 2 mcr instructions inside the critical section.
> One for the dsb() and the other for the actual function.
>
> Russell, is there a reason any of these sections should be atomic?
Under normal preempt modes those functions would end running with
preemption disabled , but with PREEMPT_RT enabled they become
preemptive .. I may have been mistaken , but my impression was that one
mcr instruction was executed and it was atomic , so there was no need
for additional protection there..
If there are two mcr instructions then you could be preempted between
the two, which may be unsafe depending on what those instructions are
doing ..
Daniel
next prev parent reply other threads:[~2007-05-23 16:32 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-05-22 23:01 Kevin Hilman
2007-05-22 23:25 ` Daniel Walker
2007-05-22 23:41 ` Kevin Hilman
2007-05-22 23:48 ` Daniel Walker
2007-05-23 9:22 ` Russell King
2007-05-23 16:13 ` Kevin Hilman
2007-05-23 16:25 ` Russell King
2007-05-23 17:31 ` Kevin Hilman
2007-05-23 16:30 ` Daniel Walker [this message]
2007-05-23 3:39 ` Thomas Gleixner
2007-05-24 0:41 ` Kevin Hilman
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