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ABdhPJyaoaOnIGiW5mF96QInJyUdWgU8IB9+8+A5dwmeq88FK5NIoagPCIjs2hg3ZiDysDU5DDBV9A== X-Received: by 2002:aca:c341:: with SMTP id t62mr2787934oif.5.1589971886521; Wed, 20 May 2020 03:51:26 -0700 (PDT) Received: from ziggy.stardust ([213.195.113.243]) by smtp.gmail.com with ESMTPSA id g90sm45950otg.75.2020.05.20.03.51.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 May 2020 03:51:25 -0700 (PDT) Subject: Re: [PATCH v2 3/4] clk / soc: mediatek: Bind clock and gpu driver for mt2701 To: Stephen Boyd , Enric Balletbo i Serra , ck.hu@mediatek.com, mark.rutland@arm.com, ulrich.hecht+renesas@gmail.com Cc: linux-kernel@vger.kernel.org, drinkcat@chromium.org, hsinyi@chromium.org, Collabora Kernel ML , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, Matthias Brugger , matthias.bgg@kernel.org, Chun-Kuang Hu , Allison Randal , Kate Stewart , Michael Turquette , Richard Fontana , Thomas Gleixner References: <20200401201736.2980433-1-enric.balletbo@collabora.com> <20200401201736.2980433-3-enric.balletbo@collabora.com> <158996963892.215346.7498020261398211458@swboyd.mtv.corp.google.com> From: Matthias Brugger Autocrypt: addr=matthias.bgg@gmail.com; prefer-encrypt=mutual; keydata= mQINBFP1zgUBEAC21D6hk7//0kOmsUrE3eZ55kjc9DmFPKIz6l4NggqwQjBNRHIMh04BbCMY fL3eT7ZsYV5nur7zctmJ+vbszoOASXUpfq8M+S5hU2w7sBaVk5rpH9yW8CUWz2+ZpQXPJcFa OhLZuSKB1F5JcvLbETRjNzNU7B3TdS2+zkgQQdEyt7Ij2HXGLJ2w+yG2GuR9/iyCJRf10Okq gTh//XESJZ8S6KlOWbLXRE+yfkKDXQx2Jr1XuVvM3zPqH5FMg8reRVFsQ+vI0b+OlyekT/Xe 0Hwvqkev95GG6x7yseJwI+2ydDH6M5O7fPKFW5mzAdDE2g/K9B4e2tYK6/rA7Fq4cqiAw1+u EgO44+eFgv082xtBez5WNkGn18vtw0LW3ESmKh19u6kEGoi0WZwslCNaGFrS4M7OH+aOJeqK fx5dIv2CEbxc6xnHY7dwkcHikTA4QdbdFeUSuj4YhIZ+0QlDVtS1QEXyvZbZky7ur9rHkZvP ZqlUsLJ2nOqsmahMTIQ8Mgx9SLEShWqD4kOF4zNfPJsgEMB49KbS2o9jxbGB+JKupjNddfxZ HlH1KF8QwCMZEYaTNogrVazuEJzx6JdRpR3sFda/0x5qjTadwIW6Cl9tkqe2h391dOGX1eOA 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x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <158996963892.215346.7498020261398211458@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/05/2020 12:13, Stephen Boyd wrote: > Quoting Enric Balletbo i Serra (2020-04-01 13:17:35) >> Now that the mmsys driver is the top-level entry point for the >> multimedia subsystem, we could bind the clock and the gpu driver on >> those devices that is expected to work, so the drm driver is >> intantiated by the mmsys driver and display, hopefully, working again. >> >> Signed-off-by: Enric Balletbo i Serra >> Reviewed-by: Chun-Kuang Hu >> --- > > Acked-by: Stephen Boyd > Now queued for v5.7-next/soc Thanks!