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[212.182.62.129]) by smtp.gmail.com with ESMTPSA id y16-20020a05651c021000b002bcda31af28sm833526ljn.42.2023.10.18.13.20.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Oct 2023 13:20:40 -0700 (PDT) Message-ID: <11b5db69-49f5-4d7b-81c9-687d66a5cb0d@linaro.org> Date: Wed, 18 Oct 2023 22:20:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/7] arm64: dts: qcom: sc7280: Fix up GPU SIDs Content-Language: en-US To: Akhil P Oommen Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Marijn Suijten , Luca Weiss , Rob Clark , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230926-topic-a643-v1-0-7af6937ac0a3@linaro.org> <20230926-topic-a643-v1-5-7af6937ac0a3@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/16/23 22:22, Akhil P Oommen wrote: > On Tue, Sep 26, 2023 at 08:24:40PM +0200, Konrad Dybcio wrote: >> >> GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). >> On platforms that support it (in firmware), it is necessary to >> describe that link, or Adreno register access will hang the board. >> >> Add that and fix up the SMR mask of SID 0, which seems to have been >> copypasted from another SoC. >> >> Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") >> Signed-off-by: Konrad Dybcio >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index c38ddf267ef5..0d96d1454c49 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2603,7 +2603,8 @@ gpu: gpu@3d00000 { >> "cx_mem", >> "cx_dbgc"; >> interrupts = ; >> - iommus = <&adreno_smmu 0 0x401>; >> + iommus = <&adreno_smmu 0 0x400>, >> + <&adreno_smmu 1 0x400>; > Aren't both functionally same? 401 works fine on sc7280. You might be > having issue due to Qcom TZ policies on your platform. I am okay with the change, but can > you please reword the commit text? Hm, looking at what the SMR registers represent, it looks like they should do the same thing and it may indeed be down to the TZ being picky.. I'll rephrase. Konrad