From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59042C433F5 for ; Mon, 27 Aug 2018 08:55:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1F79020684 for ; Mon, 27 Aug 2018 08:55:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1F79020684 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amlogic.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726921AbeH0Mku (ORCPT ); Mon, 27 Aug 2018 08:40:50 -0400 Received: from mail-sh2.amlogic.com ([58.32.228.45]:55062 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726785AbeH0Mku (ORCPT ); Mon, 27 Aug 2018 08:40:50 -0400 Received: from [10.18.16.3] (10.18.16.3) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server (TLS) id 15.0.1320.4; Mon, 27 Aug 2018 16:55:21 +0800 Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller To: Jerome Brunet , Bjorn Helgaas CC: Yue Wang , Kevin Hilman , Rob Herring , , , , , Yixun Lan , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , References: <1535096165-45827-1-git-send-email-hanjie.lin@amlogic.com> <1535096165-45827-2-git-send-email-hanjie.lin@amlogic.com> <8c48964151d24758298ba935da336c0829e2b287.camel@baylibre.com> From: Hanjie Lin Message-ID: <11d7547b-feb4-6ecb-cef3-db46ce8ee2ef@amlogic.com> Date: Mon, 27 Aug 2018 16:55:20 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <8c48964151d24758298ba935da336c0829e2b287.camel@baylibre.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.16.3] X-ClientProxiedBy: mail-sh2.amlogic.com (10.18.11.6) To mail-sh2.amlogic.com (10.18.11.6) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2018/8/24 16:22, Jerome Brunet wrote: > On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds documentation for the DT bindings in Meson PCIe >> controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 ++++++++++++++++++++++ >> 1 file changed, 63 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >> >> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >> new file mode 100644 >> index 0000000..8a831d1 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >> @@ -0,0 +1,63 @@ >> +Amlogic Meson AXG DWC PCIE SoC controller >> + >> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. >> +It shares common functions with the PCIe DesignWare core driver and >> +inherits common properties defined in >> +Documentation/devicetree/bindings/pci/designware-pci.txt. >> + >> +Additional properties are described here: >> + >> +Required properties: >> +- compatible: >> + should contain "amlogic,axg-pcie" to identify the core. >> +- reg: >> + Should contain the configuration address space. >> +- reg-names: Must be >> + - "elbi" External local bus interface registers >> + - "cfg" Meson specific registers >> + - "config" PCIe configuration space >> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. >> +- clocks: Must contain an entry for each entry in clock-names. >> +- clock-names: Must include the following entries: >> + - "pclk" PCIe GEN 100M PLL clock >> + - "port" PCIe_x(A or B) RC clock gate >> + - "general" PCIe Phy clock >> + - "mipi" PCIe_x(A or B) 100M ref clock gate >> +- resets: phandle to the reset lines. >> +- reset-names: must contain "phy" and "peripheral" >> + - "port" Port A or B reset >> + - "apb" APB reset > > The above description is not coherent (phy <=> port) > Yes, this should be port and apb here. We'll integrate phy driver into ctrl driver, and move phy reset to here also. >> + >> +Example configuration: >> + >> + pcie: pcie@f9800000 { >> + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; >> + reg = <0x0 0xf9800000 0x0 0x400000 >> + 0x0 0xff646000 0x0 0x2000 >> + 0x0 0xf9f00000 0x0 0x100000>; >> + reg-names = "elbi", "cfg", "config"; >> + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; >> + interrupts = ; >> + #interrupt-cells = <1>; >> + interrupt-map-mask = <0 0 0 0>; >> + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; >> + bus-range = <0x0 0xff>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; > > Not described above - is it even used ? > It's necessary, specified in designware-pcie.txt: - device_type: Usage: required Value type: Definition: Should be "pci". >> + phys = <&pcie_phy>; > > Not documented and not necessary. Please remove this. > We'll remove phy driver and this also. >> + ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; >> + >> + clocks = <&clkc CLKID_USB >> + &clkc CLKID_MIPI_ENABLE >> + &clkc CLKID_PCIE_A >> + &clkc CLKID_PCIE_CML_EN0>; >> + clock-names = "general", >> + "mipi", >> + "pclk", >> + "port"; >> + resets = <&reset RESET_PCIE_A>, >> + <&reset RESET_PCIE_APB>; >> + reset-names = "port", >> + "apb"; >> + }; > > > . >