From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BF9993C6606 for ; Fri, 10 Jul 2026 07:12:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783667526; cv=none; b=lRcDpDVIpBI7fRCWSgtlUhedAM6p0zXEuB2Tkr8xHBxUJfb8zs/nUrbRUQicgYEOeF1ndFp3sr+Ah7YpDovqnks9Vr8Asw2lMIX+Ex5gaNXxCiQEaTEzIPU8hv7F3Or1SSmNBgZ1T8g2cBwMVnAfuIEAqoYBebX/yRC36YEuPd8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783667526; c=relaxed/simple; bh=LIhHFkUiltZtj08irokwyO3MShHeKRDKuNGX5OJmL4g=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=usZwe8gQmg2Yg9k4tpMFjK9hkqXIcXcme9HH+WT+nL9TvNwQLIcVZRD7ozxkxTTgLVLxvWkIhdkIKedMaDHhOS3gb0yBAhwzW+X5WpFC/xc9vrrKeIno033hclth1zu0WFaBSVhEegCZF1OG+iFEXsRv3GXKdFO5nSxVBs1FY5w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pIMEfLzC; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pIMEfLzC" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A40FE1D15; Fri, 10 Jul 2026 00:11:58 -0700 (PDT) Received: from [10.174.42.251] (unknown [10.174.42.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 394E83F85F; Fri, 10 Jul 2026 00:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783667522; bh=LIhHFkUiltZtj08irokwyO3MShHeKRDKuNGX5OJmL4g=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=pIMEfLzC+3sFc/r5reUIIwXBd9bpXZCv4CGqwuO+u6xgo0AuHtSkN8bcFESPlD977 Z7QF7VwHUjUKIW6RfVi/dPjqxbVGR2pHTs8nvyNRRL1uGtahfal2QeCfBmT+xCdOsS aVQ95217l2kxlNre2HNMjexBHQLJTKXrnLv39BmA= Message-ID: <11d99a7c-50f9-4a4d-a75b-ef11cf3371af@arm.com> Date: Fri, 10 Jul 2026 12:41:57 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-7-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260708144331.679816-7-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Please do mention full register field here arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM On 08/07/26 8:13 PM, Linu Cherian wrote: > Add MMFR2 ID based BBML3 feature detection, so Ditto ^^^^^^^^^^^^ > that compliant cpus doesn't need to be added to the > midr list. Could be reworded as : Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in cpu_supports_bbml3() so that cpus with the feature would not have to be added into MIDR based supports_bbml3_list. > > Signed-off-by: Linu Cherian > --- > arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index e9ecaa036479..3f4a36f152d0 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, > > bool cpu_supports_bbml3(void) > { > + u64 mmfr2; > + > + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); > + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) > + return true; > + > /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ > static const struct midr_range supports_bbml3_list[] = { > MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), > @@ -2153,15 +2159,10 @@ bool cpu_supports_bbml3(void) > {} > }; > > - if (!is_midr_in_range_list(supports_bbml3_list)) > - return false; > - > - /* > - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care > - * about whether the MIDR check passes. > - */ > + if (is_midr_in_range_list(supports_bbml3_list)) > + return true; > > - return true; > + return false; > } > > static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) With the minor changes to the commit message above. Reviewed-by: Anshuman Khandual