From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C5C11D6DD0; Tue, 3 Sep 2024 12:44:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725367473; cv=none; b=a1MNiN8B91kDKQiqmq4pjUKBiVV63a4JD/1KiHG6meo8LgDhNZR0rHnB7HVAjAimqQU44Ic21vdhn6hIxsTHCGkYRzQY/PoBKOUis3WJPUR5x+3DPKV+iLh4qH9qKmhp9mZTENgHAJbmSXm9ly3n4erI3eus/wL49IXqySM3KO4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725367473; c=relaxed/simple; bh=CiS7TLGte5qKutCVWQk0V5K52BRWxgq5Dw+aQUFrRMg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=sE/RdtQ/Z+ZPs2O4FMiaViF2sHvMUdvOF9cd27ap9HLhRhYJ8sSNA7CgjaZrUchW2lBc0L4IjoY5UQc7+WKCmT1S/5DHxPGT2hnAsJvwHxBwLsTklwmZ/4o5KG/+eU3/Zm0rOpQc2aTk0/xPuKCmpMPRJinIVs1QAgle4XkCy54= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DpWJM6IZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DpWJM6IZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48948C4CEC7; Tue, 3 Sep 2024 12:44:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725367473; bh=CiS7TLGte5qKutCVWQk0V5K52BRWxgq5Dw+aQUFrRMg=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=DpWJM6IZUZzfXrKMMkEzA3nlQK6JFeMBV51+SmXgq6HsuUeDUFVR5a9RMXG/FDswi WaPMRHTRJvWlhRN4gspqmrC0Z0a5F6eU+d+RoysP6iyTL0F26kLV8RlDccPpKX0k7v WsaurG48wNbhFIRrQyI4yDtVcVVm8TQUYawnkXvL3q5782LToyBgrs9dL8vsri5Smd cmIzHgfgoO1JvedTr8iEvLshHGK/5ocnnpnBhVFrb2xO19QLqw91LueX0Dn8bMm7qb 3hie3Q3uxDF6W7mb0gJtIMfwf5SN9pdrD/fYuORFMfG8SNMotElSBXmT2GqRmi/+DY 9ol4VAOBmvX0g== Message-ID: <11e49954-5230-4781-8222-2e3360012c37@kernel.org> Date: Tue, 3 Sep 2024 14:44:25 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/2] coresight: cti: Add Qualcomm extended CTI support To: Mao Jinlong , Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20240903121847.6964-1-quic_jinlmao@quicinc.com> <20240903121847.6964-3-quic_jinlmao@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 03/09/2024 14:18, Mao Jinlong wrote: > The QCOM extended CTI is a heavily parameterized version of ARM’s CSCTI. > It allows a debugger to send to trigger events to a processor or to send > a trigger event to one or more processors when a trigger event occurs > on another processor on the same SoC, or even between SoCs. For Qualcomm > extended CTI, it supports up to 128 triggers. > > Signed-off-by: Mao Jinlong > --- > .../hwtracing/coresight/coresight-cti-core.c | 75 +++++++---- > .../coresight/coresight-cti-platform.c | 16 ++- > .../hwtracing/coresight/coresight-cti-sysfs.c | 124 ++++++++++++++---- > drivers/hwtracing/coresight/coresight-cti.h | 123 +++++++++++------ > 4 files changed, 239 insertions(+), 99 deletions(-) > > /* > - * Device registers > - * 0x000 - 0x144: CTI programming and status > - * 0xEDC - 0xEF8: CTI integration test. > - * 0xF00 - 0xFFC: Coresight management registers. > + * CTI CSSoc 600 has a max of 32 trigger signals per direction. > + * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. > + * Max of in and out defined in the DEVID register. > + * - pick up actual number used from .dts parameters if present. > */ > -/* CTI programming registers */ > +#define CTIINOUTEN_MAX 128 > + > #define CTICONTROL 0x000 > -#define CTIINTACK 0x010 > -#define CTIAPPSET 0x014 > -#define CTIAPPCLEAR 0x018 > -#define CTIAPPPULSE 0x01C > -#define CTIINEN(n) (0x020 + (4 * n)) > -#define CTIOUTEN(n) (0x0A0 + (4 * n)) > -#define CTITRIGINSTATUS 0x130 > -#define CTITRIGOUTSTATUS 0x134 > -#define CTICHINSTATUS 0x138 > -#define CTICHOUTSTATUS 0x13C > -#define CTIGATE 0x140 > -#define ASICCTL 0x144 > -/* Integration test registers */ > -#define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/ > -#define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/ > -#define ITCHOUT 0xEE4 /* WO RW-600 */ > -#define ITTRIGOUT 0xEE8 /* WO RW-600 */ > -#define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/ > -#define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/ > -#define ITCHIN 0xEF4 /* RO */ > -#define ITTRIGIN 0xEF8 /* RO */ > + > /* management registers */ > #define CTIDEVAFF0 0xFA8 > #define CTIDEVAFF1 0xFAC > > -/* > - * CTI CSSoc 600 has a max of 32 trigger signals per direction. > - * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. > - * Max of in and out defined in the DEVID register. > - * - pick up actual number used from .dts parameters if present. > - */ > -#define CTIINOUTEN_MAX 32 > +static const int cti_normal_offset[] = { Uh? Why do you add data definitions into header? These NEVER go to headers, for obvious reasons. > + 0x010, /* CTIINTACK */ > /** > * Group of related trigger signals > @@ -67,7 +109,7 @@ > */ > struct cti_trig_grp { > int nr_sigs; > - u32 used_mask; > + DECLARE_BITMAP(used_mask, CTIINOUTEN_MAX); > int sig_types[]; > }; > > @@ -146,9 +188,9 @@ struct cti_config { > bool hw_powered; > > /* registered triggers and filtering */ > - u32 trig_in_use; > - u32 trig_out_use; > - u32 trig_out_filter; > + DECLARE_BITMAP(trig_in_use, CTIINOUTEN_MAX); > + DECLARE_BITMAP(trig_out_use, CTIINOUTEN_MAX); > + DECLARE_BITMAP(trig_out_filter, CTIINOUTEN_MAX); > bool trig_filter_enable; > u8 xtrig_rchan_sel; > > @@ -179,6 +221,7 @@ struct cti_drvdata { > struct cti_config config; > struct list_head node; > void (*csdev_release)(struct device *dev); > + bool is_extended_cti; Why different indentation than everything else there? Please write code consistent with existing style. Best regards, Krzysztof