From: Shaohua Li <shaohua.li@intel.com>
To: Valdis.Kletnieks@vt.edu
Cc: lkml <linux-kernel@vger.kernel.org>,
linux-pci <linux-pci@atrey.karlin.mff.cuni.cz>,
Greg KH <greg@kroah.com>,
"Pallipadi, Venkatesh" <venkatesh.pallipadi@intel.com>,
"Kok, Auke" <auke-jan.h.kok@intel.com>
Subject: Re: [PATCH]PCIE ASPM support - takes 2
Date: Wed, 16 Jan 2008 13:26:14 +0800 [thread overview]
Message-ID: <1200461174.26885.4.camel@sli10-desk.sh.intel.com> (raw)
In-Reply-To: <24456.1200455812@turing-police.cc.vt.edu>
On Tue, 2008-01-15 at 22:56 -0500, Valdis.Kletnieks@vt.edu wrote:
> On Tue, 15 Jan 2008 13:02:26 +0800, Shaohua Li said:
>
> > In my test, power difference between powersave mode and performance mode
> > is about 1.3w in a system with 3 PCIE links.
>
> Do you have any numbers on what the added latency is for powersave mode, and
> a rough idea of how quickly chipsets will drop to low-power? It may affect
> usability a lot if it's "adds 10ms latency after 100ms idle" or "adds 100ms
> latency after 5 seconds idle" or some other pattern...
>
> (The chipset in my laptop claims to be an 82801G with 4 PCI-Express ports on
> it - I'm trying to get a rough idea what usage I'd get out of that feature..)
No, I thought to get the latency impact with ASPM enabled, but haven't
found a way to measure it. This is why the default setting of ASPM
currently is using BIOS setting.
Thanks,
Shaohua
next prev parent reply other threads:[~2008-01-16 5:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-15 5:02 Shaohua Li
2008-01-16 3:56 ` Valdis.Kletnieks
2008-01-16 5:26 ` Shaohua Li [this message]
2008-01-16 9:31 ` Valdis.Kletnieks
[not found] <1200367276.20538.1.camel@sli10-desk.sh.intel.com>
[not found] ` <20080115041943.GS18741@parisc-linux.org>
2008-01-15 5:07 ` Shaohua Li
2008-01-15 12:22 ` Matthew Wilcox
2008-01-16 1:14 ` Shaohua Li
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