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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-64165b2aa03sm10031978a12.6.2025.11.12.03.07.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 03:07:45 -0800 (PST) Message-ID: <1202b66c-6d4f-4909-a010-7e5e3ec7f0c7@oss.qualcomm.com> Date: Wed, 12 Nov 2025 12:07:41 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 14/21] drm/msm/adreno: Support AQE engine To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-14-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251110-kaana-gpu-support-v2-14-bef18acd5e94@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA4OSBTYWx0ZWRfX77ZJ3BLoJqNx vqh5s9gxpNTz9iTMPJ3/a3erzQaiPLQDq/JczRaJ0Knj7JoXvJBmZ2Io7FRt2TAI3+ybPfrlJHh wEWRgJ7XyuD7S0RPM/Xfx4fQvzSugDHbFWoBCIlXSiPMRxwR8n6vXTgXKE7W9jX8h8kUkbjqCBu ej+/6GUw5428Ovu1CRt/9Yo0Ijknx+w2FbFRLP+v6PWhnfKAvFvx2n7c9cxdFTkw3uddB0rFeAi lNgdTihItu5bTSY4Nw3KRQkMb+2T0j7EfmC18YWjP+fxyFizbjNCUZRQ7EYOZQ8g6SVOUBWdop+ v9ptePedaBl8eZQ6argpxqEROMrQdES1muDyM9jOhmD4a/7OaD13wbQTYaulyHL9dE8OBWZb3r+ yvYiwSDqtTHSW1KQF/ToPSckmvSNdA== X-Proofpoint-ORIG-GUID: bwZlLbq74dNcMi9ahguLSrt4pwhKD23s X-Authority-Analysis: v=2.4 cv=dZONHHXe c=1 sm=1 tr=0 ts=69146a83 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XSWwlsXGtsdNaMXbhvkA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-GUID: bwZlLbq74dNcMi9ahguLSrt4pwhKD23s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120089 On 11/10/25 5:37 PM, Akhil P Oommen wrote: > AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides > in Raytracing related workloads. Add support for loading the AQE firmware > and initialize the necessary registers. > > Since AQE engine has dependency on preemption context records, expose > Raytracing support to userspace only when preemption is enabled. > > Signed-off-by: Akhil P Oommen > --- Side question: is the AQE fully functional on any gen7 targets? A750? [...] > - adreno_gpu->has_ray_tracing = > - !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); > + /* > + * AQE requires preemption records, so disable raytracing > + * if preemption is not supported > + */ > + if (gpu->nr_rings == 1) "nr_rings > 1"? > + adreno_gpu->has_ray_tracing = > + !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); > } else if (adreno_is_a740(adreno_gpu)) { > /* Raytracing is always enabled on a740 */ > adreno_gpu->has_ray_tracing = true; > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index b507ff4e1756..7921b4a68937 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -58,6 +58,8 @@ struct a6xx_gpu { > > struct drm_gem_object *sqe_bo; > uint64_t sqe_iova; > + struct drm_gem_object *aqe_bo; > + uint64_t aqe_iova; > > struct msm_ringbuffer *cur_ring; > struct msm_ringbuffer *next_ring; > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index 78dcb9bc3377..2ef69161f1d0 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -616,6 +616,9 @@ static int hw_init(struct msm_gpu *gpu) > goto out; > > gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); > + if (a6xx_gpu->aqe_iova) > + gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova); I believe you should also set CP_AQE_APRIV_CNTL per-pipe Should we also enable AQE1 while at it, to reduce potential backwards compatibility issues? Would that require solving the iommu woes? Konrad