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Fri, 30 Jan 2026 05:20:43 -0800 (PST) X-Received: by 2002:a05:6a00:3e02:b0:81f:57a1:68f with SMTP id d2e1a72fcca58-823ab72de5emr3410052b3a.47.1769779242631; Fri, 30 Jan 2026 05:20:42 -0800 (PST) Received: from [10.0.0.3] ([106.222.235.0]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82379c21112sm8127449b3a.54.2026.01.30.05.20.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Jan 2026 05:20:42 -0800 (PST) Message-ID: <1204a2a4-18bb-f43b-6974-a19d238ff74b@oss.qualcomm.com> Date: Fri, 30 Jan 2026 18:50:35 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v3 2/7] media: iris: introduce SM8350 and SC8280XP support Content-Language: en-US To: Dmitry Baryshkov , Konrad Dybcio Cc: Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Abhinav Kumar , Bjorn Andersson , David Heidelberg , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold References: <20260125-iris-sc8280xp-v3-0-d21861a9ea33@oss.qualcomm.com> <20260125-iris-sc8280xp-v3-2-d21861a9ea33@oss.qualcomm.com> From: Dikshita Agarwal In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: FOuu8JOTR2TFYtzvydGmknd8W4ya0bYM X-Proofpoint-ORIG-GUID: FOuu8JOTR2TFYtzvydGmknd8W4ya0bYM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTMwMDEwOSBTYWx0ZWRfX5aq71xyMw1Ui SQSdryvlHyRVfv2BWYuGHnEO27260Qx+g6nBDMZHiJF6Y35TjsIvMpYdzYRpwLqm6HjnMl8/lXq BMwPgu127oTpwHRBHxaXi27GWiArpZoMV5O+Rcu0iMKYMvlWyBnc6g9rd8BSJQVCOpDd+uiXd56 +JKZeAqjpVfLQGRKkMty0suVE92QwT4NV0KJxia5SLE8L0MTXOvHBPFh0Na+HEYBjLEj3VdurmR /Ubosx3MFZLN+HqahCR45Kyu0f1yENmAecp7jyrdDtyJbtqPLu+lbnDPvVue98bIOlxGFfume8n ot/xwJFwhnCRc3qrtKA7Ci4JRLJYlD61l3pszuMU+UA6RqZ5YOWz77b+OuXjHsTB+AonjtJ1exA Z87SdwrRE1FJ8vzUPYo8JA2+5adgQ82Md7uNT3Qwz1BWGRnshH9Dz5OBlPkQrvLjlM3ChfCTfqc 1UeIY+CXQufXcrje5aA== X-Authority-Analysis: v=2.4 cv=G5cR0tk5 c=1 sm=1 tr=0 ts=697cb02c cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=6cH4IgXjao/mkWo6W7aGpA==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=i3vytz1KKoUbyb35L_EA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-01-30_01,2026-01-29_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601300109 On 1/26/2026 4:25 PM, Dmitry Baryshkov wrote: > On Mon, Jan 26, 2026 at 10:50:56AM +0100, Konrad Dybcio wrote: >> On 1/25/26 4:32 PM, Dmitry Baryshkov wrote: >>> SM8350 and SC8280XP have an updated version of the Iris2 core also >>> present on the SM8250 and SC7280 platforms. Add necessary platform data >>> to utilize the core on those two platforms. >>> >>> The iris_platform_gen1.c is now compiled unconditionally, even if Venus >>> driver is enabled, but SM8250 and SC7280 are still disabled in >>> iris_dt_match. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >> >> [...] >> >>> +static void iris_set_sm8350_preset_registers(struct iris_core *core) >>> +{ >>> + u32 val; >>> + >>> + val = readl(core->reg_base + 0xb0088); >>> + val &= ~0x11; >>> + writel(val, core->reg_base + 0xb0088); >> >> Can we "open-source" what this write does? > > I'd leave this question to Vikash. Hopefully he can comment if I can > open these bits or not. This register controls the clock halt states for several IRIS sub‑cores. A bit value of 1 halts the clock, and 0 enables it. During power‑on, we clear bits 0 and 4 to unhalt/enable the corresponding core clocks. Thanks, Dikshita >