From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762499AbZE0H13 (ORCPT ); Wed, 27 May 2009 03:27:29 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1761194AbZE0HZZ (ORCPT ); Wed, 27 May 2009 03:25:25 -0400 Received: from claw.goop.org ([74.207.240.146]:33612 "EHLO claw.goop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762125AbZE0HZX (ORCPT ); Wed, 27 May 2009 03:25:23 -0400 From: Jeremy Fitzhardinge To: Ingo Molnar Cc: the arch/x86 maintainers , Linux Kernel Mailing List , Xen-devel , Greg KH , Jens Axboe , Chris Wright , kurt.hackel@oracle.com, Andrew Morton , Ky Srinivasan , Beulich , Linus Torvalds , Matthew Wilcox , Jesse Barnes , Alex Nixon , Jeremy Fitzhardinge Subject: [PATCH 05/10] x86/PCI: Clean up pci_cache_line_size Date: Wed, 27 May 2009 00:24:37 -0700 Message-Id: <1243409082-21349-6-git-send-email-jeremy@goop.org> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <1243409082-21349-1-git-send-email-jeremy@goop.org> References: <1243409082-21349-1-git-send-email-jeremy@goop.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alex Nixon Separate out x86 cache_line_size initialisation code into its own function (so it can be shared by Xen later in this patch series) [ Impact: cleanup ] Signed-off-by: Alex Nixon Signed-off-by: Jeremy Fitzhardinge Reviewed-by: "H. Peter Anvin" Reviewed-by: Matthew Wilcox Reviewed-by: Jesse Barnes --- arch/x86/include/asm/pci_x86.h | 1 + arch/x86/pci/common.c | 17 +++++++++++------ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index e60fd3e..5401ca2 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -45,6 +45,7 @@ enum pci_bf_sort_state { extern unsigned int pcibios_max_latency; void pcibios_resource_survey(void); +void pcibios_set_cache_line_size(void); /* pci-pc.c */ diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 2202b62..011ff45 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -412,26 +412,31 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum) extern u8 pci_cache_line_size; -int __init pcibios_init(void) +void __init pcibios_set_cache_line_size(void) { struct cpuinfo_x86 *c = &boot_cpu_data; - if (!raw_pci_ops) { - printk(KERN_WARNING "PCI: System does not support PCI\n"); - return 0; - } - /* * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8 * and P4. It's also good for 386/486s (which actually have 16) * as quite a few PCI devices do not support smaller values. */ + pci_cache_line_size = 32 >> 2; if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD) pci_cache_line_size = 64 >> 2; /* K7 & K8 */ else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL) pci_cache_line_size = 128 >> 2; /* P4 */ +} + +int __init pcibios_init(void) +{ + if (!raw_pci_ops) { + printk(KERN_WARNING "PCI: System does not support PCI\n"); + return 0; + } + pcibios_set_cache_line_size(); pcibios_resource_survey(); if (pci_bf_sort >= pci_force_bf) -- 1.6.0.6