From: Ruidong Tian <tianruidong@linux.alibaba.com>
To: Borislav Petkov <bp@alien8.de>
Cc: catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org,
guohanjun@huawei.com, sudeep.holla@arm.com,
xueshuai@linux.alibaba.com, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
rafael@kernel.org, lenb@kernel.org, tony.luck@intel.com,
yazen.ghannam@amd.com, misono.tomohiro@fujitsu.com,
fengwei_yin@linux.alibaba.com
Subject: Re: [PATCH v5 00/17] ARM Error Source Table V2 Support
Date: Fri, 9 Jan 2026 20:26:27 +0800 [thread overview]
Message-ID: <1243a296-f018-42f8-9c07-297862fb0f4a@linux.alibaba.com> (raw)
In-Reply-To: <20260109103416.GAaWDZqDYoyt3KRAE9@fat_crate.local>
在 2026/1/9 18:34, Borislav Petkov 写道:
> On Mon, Jan 05, 2026 at 05:12:25PM +0800, Ruidong Tian wrote:
>>> What is a "RAS node"?
>> A RAS node is the hardware interface for error reporting and control,
>> consisting of one or more register sets (a collection of RAS records). It is
>> responsible for error logging and interrupt signaling[0].
>
> OMG, one more meaning for the word "node". Because we're not ambiguous enough.
>
> /facepalm
>
>> A single hardware component can feature multiple RAS nodes. For example, a
>> memory controller is treated as a "RAS device", where each memory channel
>> has its own RAS node. Interrupts generated by these nodes are typically
>> aggregated into a single interrupt line managed at the RAS device level.
>
> Nomenclaturial tragedy, I'd say.
>
>> Comparison with x86 MCA:
>>
>> RAS record ≈ MCA bank.
>> RAS node ≈ A set of MCA banks + CMCI on a core.
>>
>> The key difference lies in uncore handling: x86 typically maps uncore errors
>> (like those from a memory controller) into core-based MCA banks. In
>> contrast, ARM requires uncore components to provide their own standalone RAS
>> nodes. When a component requires multiple such nodes, they are grouped and
>> managed as a "RAS device" in AEST driver.
>>
>> [0]: https://developer.arm.com/documentation/ihi0100/latest
>
> Yah, thanks for explaining.
>
>>> The ATL is very AMD-specific. What does "conceptually similar" mean exactly?
>> By "conceptually similar," I mean that both ARM and AMD share the same
>> functional requirement: translating between a System Physical Address (SPA)
>> and a device-specific address (like a DRAM address) for RAS purposes.
>>
>> The goal here is not to share the hardware-specific translation logic, but
>> to provide a unified interface (an abstraction layer). The actual
>> implementation of the translation remains entirely architecture-specific.
>
> And why do we need an arch-overlapping unified interface?
>
> You can just as well have aest_convert_la_to_spa() and none of that "unifying"
> churn.
>
You're right, that would be much cleaner. I was trying too hard to keep
the interface unified across architectures. I'll drop the unified
interface and use a direct helper instead in next version. Thanks for
the feedback!
prev parent reply other threads:[~2026-01-09 12:26 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-30 9:09 Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 01/17] ACPI/AEST: Parse the AEST table Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 02/17] ras: AEST: Add probe/remove for AEST driver Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 03/17] ras: AEST: support different group format Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 04/17] ras: AEST: Unify the read/write interface for system and MMIO register Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 05/17] ras: AEST: Probe RAS system architecture version Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 06/17] ras: AEST: Support RAS Common Fault Injection Model Extension Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 07/17] ras: AEST: Support CE threshold of error record Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 08/17] ras: AEST: Enable and register IRQs Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 09/17] ras: AEST: Add cpuhp callback Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 10/17] ras: AEST: Introduce AEST driver sysfs interface Ruidong Tian
2025-12-30 9:09 ` [PATCH v5 11/17] ras: AEST: Add error count tracking and debugfs interface Ruidong Tian
2025-12-30 9:12 ` [PATCH v5 12/17] ras: AEST: Allow configuring CE threshold via debugfs Ruidong Tian
2025-12-30 9:13 ` [PATCH v5 13/17] ras: AEST: Introduce AEST inject interface to test AEST driver Ruidong Tian
2025-12-30 9:13 ` [PATCH v5 14/17] ras: ATL: Unify ATL interface for ARM64 and AMD Ruidong Tian
2025-12-30 9:13 ` [PATCH v5 15/17] ras: AEST: Add framework to process AEST vendor node Ruidong Tian
2025-12-30 9:13 ` [PATCH v5 16/17] ras: AEST: support vendor node CMN700 Ruidong Tian
2026-01-02 16:51 ` kernel test robot
2026-01-02 17:43 ` kernel test robot
2025-12-30 9:13 ` [PATCH v5 17/17] trace, ras: add ARM RAS extension trace event Ruidong Tian
2025-12-30 20:22 ` [PATCH v5 00/17] ARM Error Source Table V2 Support Borislav Petkov
2026-01-05 9:12 ` Ruidong Tian
2026-01-09 10:34 ` Borislav Petkov
2026-01-09 12:26 ` Ruidong Tian [this message]
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