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Subject: Re: [PATCH 8/15] sched: Add parameter sched_mn_power_savings to
 control MN domain sched policy
From: Peter Zijlstra <peterz@infradead.org>
To: svaidy@linux.vnet.ibm.com
Cc: Andreas Herrmann <andreas.herrmann3@amd.com>, Ingo Molnar <mingo@elte.hu>,
       linux-kernel@vger.kernel.org, Gautham Shenoy <ego@in.ibm.com>,
       Srivatsa Vaddagiri <vatsa@in.ibm.com>,
       Dipankar Sarma <dipankar@in.ibm.com>,
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Date: Mon, 24 Aug 2009 17:45:14 +0200
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On Mon, 2009-08-24 at 21:02 +0530, Vaidyanathan Srinivasan wrote:
> * Peter Zijlstra <peterz@infradead.org> [2009-08-24 16:56:18]:
> 
> > On Thu, 2009-08-20 at 15:39 +0200, Andreas Herrmann wrote:
> > > Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
> > > ---
> > 
> > > +#ifdef CONFIG_SCHED_MN
> > > +	if (!err && mc_capable())
> > > +		err = sysfs_create_file(&cls->kset.kobj,
> > > +					&attr_sched_mn_power_savings.attr);
> > > +#endif
> > 
> > *sigh* another crappy sysfs file
> > 
> > Guys, can't we come up with anything better than sched_*_power_saving=n?
> > 
> > This configuration space is _way_ too large, and now it gets even
> > crazier.
> 
> Hi Peter and Andreas,
> 
> Actually we had sched_power_savings and related simplifications, but
> that did not really simplify the interface.

Well, I prefer a single sched_power knob that either goes on or off.

A user really isn't interested in exploring a 3^3 configuration space
{PERF, POWER, POWER-WAKE-BALANCE} x {SMT, MC, MN} in order to find what
works best.

> As for this mulit-node MN stuff, Gautham had posted a better solution
> to propagate the sched_mc flags without need for new sysfs file and
> related changes.
> 
> Please take a look at: http://lkml.org/lkml/2009/3/31/137 and
> http://lkml.org/lkml/2009/3/31/142 which actually degenerates the
> domain.

Ah, right, that got lost in my inbox :/ Let me go read those too.

> However Andreas's requirement seem to indicate multiple nodes within
> a single socket.  I did not yet completely understand that topology.
> Some for of smart degeneration may save an additional tunable here.

Yes, apparently AMD is going to put multiple nodes in a single socket,
not sure how they do that, Andreas do these chips have multiple memory
busses?

I was thinking chips were pin constrained and wouldn't add a whole
second memory interface to the package, but what do I know...