From: Catalin Marinas <catalin.marinas@arm.com>
To: "Kirill A. Shutemov" <kirill@shutemov.name>
Cc: Russell King <linux@arm.linux.org.uk>,
Siarhei Siamashka <siarhei.siamashka@nokia.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Aaro Koskinen <aaro.koskinen@nokia.com>,
Valdis.Kletnieks@vt.edu
Subject: Re: [PATCH v2] [RESEND] Handle instruction cache maintenance fault properly
Date: Wed, 12 May 2010 12:01:27 +0100 [thread overview]
Message-ID: <1273662087.23818.63.camel@e102109-lin.cambridge.arm.com> (raw)
In-Reply-To: <AANLkTilVp0xvAJNns3TEe4SzEUpN8hMC9DdwmwW7i9yX@mail.gmail.com>
On Tue, 2010-05-11 at 11:33 +0100, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.
>
> In ARMv6 "external abort on linefetch" replaced by "instruction cache
> maintenance fault". Let's handle it as translation fault. It fixes the
> issue.
>
> I'm not sure if it's reasonable to check arch version in run-time.
> Let's do it in compile time for now.
>
> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
> Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
FWIW:
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
--
Catalin
next prev parent reply other threads:[~2010-05-12 11:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-11 10:33 Kirill A. Shutemov
2010-05-12 11:01 ` Catalin Marinas [this message]
2010-05-14 13:29 ` Catalin Marinas
2011-12-15 21:56 ` Uwe Kleine-König
2011-12-16 2:22 ` Kirill A. Shutemov
2011-12-16 10:01 ` Uwe Kleine-König
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