perf, how to support multiple x86 hw pmus?

[Lin Ming <ming.m.lin@intel.com>]

Hi, all

Here multiple x86 hw pmus means, for example, Intel "core" and "uncore"
pmu. "core" pmu is to collect per cpu data, cpu-cycles, branch-misses,
etc. "uncore" pmu is to collect per package data, L3 cache, Intel QPI,
integrated memory controller, etc.

I am going to add Intel uncore pmu support to perf. To reduce code
duplicate, "uncore" pmu should reuse most of the "core" pmu code. But
currently, the x86 core pmu code(arch/x86/kernel/cpu/perf_event.c) only
supports one pmu, with a definition as below.

static struct x86_pmu x86_pmu __read_mostly;

Many functions use above global definition "x86_pmu". It seems to me
that we need to re-structure x86 pmu code to support multiple hw pmus.

Any idea?

Thanks,
Lin Ming