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Mon, 09 Mar 2026 20:53:27 -0700 (PDT) X-Received: by 2002:a05:6a20:394a:b0:398:7949:38fb with SMTP id adf61e73a8af0-39879494e67mr8280804637.54.1773114807109; Mon, 09 Mar 2026 20:53:27 -0700 (PDT) Received: from [10.217.217.147] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c739e184f92sm11379844a12.28.2026.03.09.20.53.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Mar 2026 20:53:26 -0700 (PDT) Message-ID: <12855948-936f-4762-aff2-1777bcaa5638@oss.qualcomm.com> Date: Tue, 10 Mar 2026 09:23:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: clock: qcom: glymur-gcc: Add missing CX power domain and required opp To: Abel Vesa , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Maulik Shah , Dmitry Baryshkov , Jyothi Kumar Seerapu , Konrad Dybcio Cc: Krzysztof Kozlowski , Sibi Sankar , Pankaj Patil , Akhil P Oommen , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jishnu Prakash , Raviteja Laggyshetty , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi References: <20260309-glymur-fix-gcc-cx-scaling-v1-0-f682c82f116f@oss.qualcomm.com> <20260309-glymur-fix-gcc-cx-scaling-v1-1-f682c82f116f@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <20260309-glymur-fix-gcc-cx-scaling-v1-1-f682c82f116f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=cZ/fb3DM c=1 sm=1 tr=0 ts=69af95b8 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=g3FZPDIDENTUAh6yQDIA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: BqAwvQdglhKJE6kW4eEIo9obMv-9ycxc X-Proofpoint-GUID: BqAwvQdglhKJE6kW4eEIo9obMv-9ycxc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEwMDAyOCBTYWx0ZWRfXwnpgFrPtaAA/ sOp+C0gNAX8YjnRaT7N3CCzZsRcSkFqWQ9pp4TUZiISeHf6Aa3O/PUSkmscIU+D9DFUG/NQpwht pOTf+lrY2vLV24UIdbdUIXYVM3j+ub5WsAt67EV8hPS1R+MZIw6/OWT5nNirUGjOonBLZGAlAZN G3NLBOOSJlIvEJktQ23WM6wCyZaDNbRJlOInUcmiUoOBNKkW18/JdBu/VxQU3dZbnICq/gFO6Mk pJCuyuqifQ08z37WIAE8F175b2PTg+uwbPwRIPOq+bvCVjpiwPoR3mKLdkpW5teXoAml74Gvo17 KfeTxMEnlEZp/foOrXqBM5WVypByR7yuSZVsXkZN7URNCO158TKk9ol7L5DKAWVtM3fWp9FD2Ug 2hMKfU5y3apusGT63uQviaSSbndHd5RxTuX2kRKiY0Hpr0Kmf5gaN44yGrYcW9EcrpIcEmh5Se7 I3DS+QLmmjX9XHBjFyA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_01,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603100028 On 3/9/2026 3:36 PM, Abel Vesa wrote: > It has been concluded off-list that the Global Clock Controller needs to > scale the RPMh CX power domain, otherwise some of the subsystems might > crash or be unstable. So adding the RPMh CX power domain to the clock > controller which will result in all GDSCs being parented by CX. This way, > the vote from the consumers of each GDSC will trickle all the way to CX. > Are the consumers not taking care to vote on clocks to take care? GDSCs from design of hardware, never requires a vote to operate. It is the clocks which has a voltage requirements. > So document the power domain and the required opp to that end. > > Fixes: ee2d967030fe ("dt-bindings: clock: qcom: document the Glymur Global Clock Controller") > Signed-off-by: Abel Vesa > --- > .../devicetree/bindings/clock/qcom,glymur-gcc.yaml | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml > index b05b0e6c4483..94a911855776 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml > @@ -65,9 +65,20 @@ properties: > - description: USB4 PHY 2 pcie pipe clock source > - description: USB4 PHY 2 Max pipe clock source > > + power-domains: > + description: > + A phandle and PM domain specifier for the CX power domain. > + maxItems: 1 > + > + required-opps: > + description: > + A phandle to an OPP node describing required CX performance point. > + maxItems: 1 > + > required: > - compatible > - clocks > + - power-domains > - '#power-domain-cells' > > allOf: > @@ -78,6 +89,7 @@ unevaluatedProperties: false > examples: > - | > #include > + #include > clock-controller@100000 { > compatible = "qcom,glymur-gcc"; > reg = <0x100000 0x1f9000>; > @@ -113,6 +125,8 @@ examples: > <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>, > <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>, > <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>; > + power-domains = <&rpmhpd RPMHPD_CX>; > + required-opps = <&rpmhpd_opp_nom>; > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > -- Thanks, Taniya Das