From: Hans Rosenfeld <hans.rosenfeld@amd.com>
To: <hpa@zytor.com>, <tglx@linutronix.de>, <mingo@elte.hu>
Cc: <linux-kernel@vger.kernel.org>, <andreas.herrmann3@amd.com>,
Hans Rosenfeld <hans.rosenfeld@amd.com>
Subject: [PATCH 0/4] x86, amd: family 0x15 L3 cache features
Date: Mon, 20 Dec 2010 18:13:43 +0100 [thread overview]
Message-ID: <1292865227-647466-1-git-send-email-hans.rosenfeld@amd.com> (raw)
This patch set applies to tip/x86/amd-nb f658bcfb. It enables L3 cache
index disable and adds support for L3 cache partitioning on family 0x15
CPUs.
Andreas Herrmann (1):
x86, amd: Normalize compute unit IDs on multi-node processors
Hans Rosenfeld (3):
x86, amd: Enable L3 cache index disable on family 0x15
x86, amd: Extend AMD northbridge caching code to support "Link
Control" devices
x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs
arch/x86/include/asm/amd_nb.h | 4 ++
arch/x86/kernel/amd_nb.c | 69 ++++++++++++++++++++++++++++++-
arch/x86/kernel/cpu/amd.c | 8 +++-
arch/x86/kernel/cpu/intel_cacheinfo.c | 73 +++++++++++++++++++++++++++-----
arch/x86/kernel/smpboot.c | 1 +
include/linux/pci_ids.h | 1 +
6 files changed, 140 insertions(+), 16 deletions(-)
next reply other threads:[~2010-12-20 17:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-20 17:13 Hans Rosenfeld [this message]
2010-12-20 17:13 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld
2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
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