From: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org, ralf@linux-mips.org,
linux-kernel@vger.kernel.org
Cc: David Daney <ddaney@caviumnetworks.com>
Subject: [PATCH 2/6] MIPS: Add accessor macros for 64-bit performance counter registers.
Date: Thu, 6 Jan 2011 18:35:03 -0800 [thread overview]
Message-ID: <1294367707-2593-3-git-send-email-ddaney@caviumnetworks.com> (raw)
In-Reply-To: <1294367707-2593-1-git-send-email-ddaney@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/include/asm/mipsregs.h | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index d5c9eaa..86c7ec1 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1019,18 +1019,26 @@ do { \
#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
+#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
+#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
+#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
+#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
+#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
+#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
+#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
+#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
/* RM9000 PerfCount performance counter register */
#define read_c0_perfcount() __read_64bit_c0_register($25, 0)
--
1.7.2.3
next prev parent reply other threads:[~2011-01-07 2:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-07 2:35 [PATCH 0/6] MIPS: perf: Make perf work for 64-bit/Octeon counters David Daney
2011-01-07 2:35 ` [PATCH 1/6] MIPS: Octeon: Enable per-CPU IRQs on all CPUs David Daney
2011-01-07 2:35 ` David Daney [this message]
2011-01-07 2:35 ` [PATCH 3/6] MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c David Daney
2011-01-07 2:35 ` [PATCH 4/6] MIPS: perf: Reorganize contents of perf support files David Daney
2011-01-20 10:01 ` Deng-Cheng Zhu
2011-01-20 17:51 ` David Daney
2011-01-07 2:35 ` [PATCH 5/6] MIPS: perf: Add support for 64-bit perf counters David Daney
2011-01-20 10:06 ` Deng-Cheng Zhu
2011-01-20 17:48 ` David Daney
2011-01-07 2:35 ` [PATCH 6/6] MIPS: perf: Add Octeon support for hardware perf David Daney
2011-01-20 9:59 ` [PATCH 0/6] MIPS: perf: Make perf work for 64-bit/Octeon counters Deng-Cheng Zhu
2011-01-20 17:55 ` David Daney
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