From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753489Ab1AYNT3 (ORCPT ); Tue, 25 Jan 2011 08:19:29 -0500 Received: from service87.mimecast.com ([94.185.240.25]:60897 "HELO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1753124Ab1AYNT2 convert rfc822-to-8bit (ORCPT ); Tue, 25 Jan 2011 08:19:28 -0500 Subject: Re: [PATCH] ARM: vfp: Fix up exception location in Thumb mode From: Catalin Marinas To: Russell King - ARM Linux Cc: Colin Cross , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org In-Reply-To: <20110123155157.GD30094@n2100.arm.linux.org.uk> References: <20110114120229.GA15996@n2100.arm.linux.org.uk> <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> <20110114154919.GE15996@n2100.arm.linux.org.uk> <1295022193.7901.56.camel@e102109-lin.cambridge.arm.com> <20110114163520.GH15996@n2100.arm.linux.org.uk> <1295024327.7901.70.camel@e102109-lin.cambridge.arm.com> <20110114173050.GJ15996@n2100.arm.linux.org.uk> <20110115154019.GF15996@n2100.arm.linux.org.uk> <20110123155157.GD30094@n2100.arm.linux.org.uk> Organization: ARM Limited Date: Tue, 25 Jan 2011 13:19:17 +0000 Message-ID: <1295961557.10109.253.camel@e102109-lin.cambridge.arm.com> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-OriginalArrivalTime: 25 Jan 2011 13:19:22.0238 (UTC) FILETIME=[7AD779E0:01CBBC92] X-MC-Unique: 111012513192407501 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 2011-01-23 at 15:51 +0000, Russell King - ARM Linux wrote: > On Sun, Jan 16, 2011 at 11:49:21AM +0000, Catalin Marinas wrote: > > On Saturday, 15 January 2011, Russell King - ARM Linux > > wrote: > > > It's a reveq, so I thought we should cover all the instructions with > > > an 'eq' conditional for thumb. > > > > If the it instruction doesn't cover all instructions, gas generates > > some more its. But in this case, for little endian, the it instruction > > covers more since reveq isn't included and having the beq not last in > > the block I think is unpredictable. If you really want to optimise the > > big endian case not to have an additional it generated by gas, you can > > write ittt so that beq is included with little endian but not with big > > endian. I wouldn't bother much for an extra it anyway. > > I think the itttt is correct. Unless you wish to illustrate why you > think it's wrong by pasting the code and showing why you think the > beq isn't the last instruction... With your patch applied (visually), the code becomes (removed the comment before beq): tst r3, #PSR_T_BIT @ Thumb mode? itttt eq @ explicit IT needed for the 1f label subeq r4, r2, #4 @ ARM instr at LR - 4 1: ldreqt r0, [r4] #ifdef CONFIG_CPU_ENDIAN_BE8 reveq r0, r0 @ little endian instruction #endif beq call_fpe The little endian case only has 3 conditional instructions: subeq r4, r2, #4 @ ARM instr at LR - 4 1: ldreqt r0, [r4] beq call_fpe but you add itttt (if-then-then-then-then) which expects 4 conditional instructions, IOW beq is no longer the last. So cutting a 't' would sort it out (unless I misread your patch). > > > tst r3, #PSR_T_BIT > > > subeq r4, r2, #4 > > > 1: ldreqt r0, [r4] > > > reveq r0, r0 > > > beq call_fpe > > > > You can have the T bit set but the instruction a 32-bit Thumb in which > > case r2 is in the middle of such instruction rather than the next. > > Unless you only refer to the ARM mode, in which case the comment is > > fine. > > So? I'm confused why you're making a mountain out of apparantly > nothing. No issue really, the comment can stay as you wrote it (I don't read them anyway :)). -- Catalin