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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-62c018f663asm1086756a12.43.2025.09.09.04.24.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Sep 2025 04:24:03 -0700 (PDT) Message-ID: <12ae186b-9816-4269-ab3a-7aacdc7cb954@oss.qualcomm.com> Date: Tue, 9 Sep 2025 13:24:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] phy: qcom-qmp: qserdes-com: Add v8 DP-specific qserdes register offsets To: Dmitry Baryshkov , Abel Vesa Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250909-phy-qcom-edp-add-glymur-support-v2-0-02553381e47d@linaro.org> <20250909-phy-qcom-edp-add-glymur-support-v2-2-02553381e47d@linaro.org> <3xw54kzk36u7zrfhgva4p577nzle3ctzi3lyhcxapczv2bhceo@23zcaylkqoff> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <3xw54kzk36u7zrfhgva4p577nzle3ctzi3lyhcxapczv2bhceo@23zcaylkqoff> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 4nmECZaXCmOdP56HT7iYUNomooeNaSWZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzNSBTYWx0ZWRfXy88BpRNp4CJx fYKRScwfGjcrUOdVnJpx5ZwuuO/1JNk+b2UWSlG5A+esb2HYZQ9gCeFiCww9TtS/nJChZQDPayq z72cVIC4AfnCaE/8+7j9wSkLAobXa/3B9M8hsmHLgzJZruTOK3TUgM+bN1RECEAMhky4iz8IxSN 9n4uhW/2JHnXEaBaXzdRG0zIZ4k7JIizdiub3W+fH4fhTxoiVURsLkN2PlfHOZITYYKNB09Zn/3 4Km8DVqz//6oF9z2bZXKAc20+4CZrtc3azymM2T5RfShdhXdaqKF2KuZR8E5NPxyk0gclpTSMiW 4fvh0ooHpvEPj8DiyJGNrBYWo5vcTKM9Vy980eJyYwZHcTg6p9yiVfE2IfV/hWXbe6tMbvgnf1b 1qwwj9Zx X-Proofpoint-GUID: 4nmECZaXCmOdP56HT7iYUNomooeNaSWZ X-Authority-Analysis: v=2.4 cv=N8UpF39B c=1 sm=1 tr=0 ts=68c00e56 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=KKAkSRfTAAAA:8 a=hW6Tvmzh9q5i_Tc9j78A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-09_01,2025-09-08_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060035 On 9/9/25 1:19 PM, Dmitry Baryshkov wrote: > On Tue, Sep 09, 2025 at 01:07:27PM +0300, Abel Vesa wrote: >> Starting with Glymur, the PCIe and DP PHYs qserdes register offsets differ >> for the same version number. So in order to be able to differentiate >> between them, add these ones with DP prefix. >> >> Signed-off-by: Abel Vesa >> --- >> .../phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h | 52 ++++++++++++++++++++++ >> 1 file changed, 52 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h >> new file mode 100644 >> index 0000000000000000000000000000000000000000..2bef1eecdc56a75e954ebdbcd168ab7306be1302 >> --- /dev/null >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-qserdes-com-v8.h >> @@ -0,0 +1,52 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (C) 2025 Linaro Ltd. >> + */ >> + >> +#ifndef QCOM_PHY_QMP_DP_QSERDES_COM_V8_H_ >> +#define QCOM_PHY_QMP_DP_QSERDES_COM_V8_H_ >> + >> +/* Only for DP QMP V8 PHY - QSERDES COM registers */ >> +#define DP_QSERDES_V8_COM_HSCLK_SEL_1 0x03c >> +#define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x058 >> +#define DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x05c >> +#define DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0 0x060 >> +#define DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0 0x064 >> +#define DP_QSERDES_V8_COM_CP_CTRL_MODE0 0x070 >> +#define DP_QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 >> +#define DP_QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 >> +#define DP_QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c >> +#define DP_QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 >> +#define DP_QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 >> +#define DP_QSERDES_V8_COM_DEC_START_MODE0 0x088 >> +#define DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 >> +#define DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 >> +#define DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 >> +#define DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0 0x0a0 >> +#define DP_QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 >> +#define DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0 0x0a4 >> +#define DP_QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac >> +#define DP_QSERDES_V8_COM_BG_TIMER 0x0bc >> +#define DP_QSERDES_V8_COM_SSC_EN_CENTER 0x0c0 >> +#define DP_QSERDES_V8_COM_SSC_ADJ_PER1 0x0c4 >> +#define DP_QSERDES_V8_COM_SSC_PER1 0x0cc >> +#define DP_QSERDES_V8_COM_SSC_PER2 0x0d0 >> +#define DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc >> +#define DP_QSERDES_V8_COM_CLK_ENABLE1 0x0e0 >> +#define DP_QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 >> +#define DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 >> +#define DP_QSERDES_V8_COM_PLL_IVCO 0x0f4 >> +#define DP_QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 >> +#define DP_QSERDES_V8_COM_RESETSM_CNTRL 0x118 >> +#define DP_QSERDES_V8_COM_LOCK_CMP_EN 0x120 >> +#define DP_QSERDES_V8_COM_VCO_TUNE_CTRL 0x13c >> +#define DP_QSERDES_V8_COM_VCO_TUNE_MAP 0x140 >> +#define DP_QSERDES_V8_COM_CLK_SELECT 0x164 >> +#define DP_QSERDES_V8_COM_CORE_CLK_EN 0x170 >> +#define DP_QSERDES_V8_COM_CMN_CONFIG_1 0x174 > > The registers are the same at least up to this point. Would it make > sense to keep common part in the same header and define only those bits > that actually differ between DP and PCIe parts? (Is it really about PCIe > or is it eDP vs everything else?) No, there's a wild amount of variation between various "v8" PHYs and this is impossible to catch by eye Konrad