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([2a01:e0a:106d:1080:72a2:f5f2:e023:2a2e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43796ad009bsm34212046f8f.39.2026.02.17.07.40.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Feb 2026 07:40:17 -0800 (PST) Message-ID: <12f8346f-3df4-4081-a009-7a3ca83e2c36@linaro.org> Date: Tue, 17 Feb 2026 16:40:16 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH v2 0/5] PCI: qcom: Add D3cold support To: Krishna Chaitanya Chundru , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com References: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2/17/26 12:19, Krishna Chaitanya Chundru wrote: > This series adds support for putting Qualcomm PCIe host bridges into D3cold > when downstream conditions allow it, and introduces a small common helper > to determine D3cold eligibility based on endpoint state. > > On Qualcomm platforms, PCIe host controllers are currently kept powered > even when there are no active endpoints (i.e. all endpoints are already in > PCI_D3hot). This prevents the SoC from entering deeper low‑power states > such as CXPC. > > While PCIe D3cold support exists in the PCI core, host controller drivers > lack a common mechanism to determine whether it is safe to power off the > host bridge without breaking active devices or wakeup functionality. > As a result, controllers either avoid entering D3cold or depend on rough, > driver‑specific workarounds. > > This series addresses that gap. > > 1. Introduces pci_host_common_can_enter_d3cold(), a helper that determines > whether a host bridge may enter D3cold based on downstream PCIe endpoint > state. The helper permits D3cold only when all *active* endpoints are > already in PCI_D3hot, and any wakeup‑enabled endpoint supports PME > from D3cold. > > 2. Updates the Designware PCIe host driver to use this helper in the > suspend_noirq() path, replacing the existing heuristic that blocked > D3cold whenever L1 ASPM was enabled. > > 3. Enables D3cold support for Qualcomm PCIe controllers by wiring them into > the DesignWare common suspend/resume flow and explicitly powering down > controller resources when all endpoints are in D3hot. > > The immediate outcome of this series is that Qualcomm PCIe host bridges can > enter D3cold when all endpoints are in D3hot. > > This is a necessary but not sufficient step toward unblocking CXPC. With > this series applied, CXPC can be achieved on systems with no attached NVMe > devices. Support for NVMe‑attached systems requires additional changes > in NVMe driver, which are being worked on separately. > > Tested on: > - Qualcomm Lemans EVK, Monaco & sc7280 platforms. > > Validation steps: > - Boot without NVMe attach: > * PCIe host enters D3cold during suspend > * SoC is able to reach CXPC provided other drivers also remove > their votes as part of suspend. > > Signed-off-by: Krishna Chaitanya Chundru > --- > Changes in v2: > - Updated the cover letter (Bjorn Andersson) > - Add get_ltssm helper function to read LTSSM state from parf. > - Allow D3cold if there is no driver enabled for a endpoint. > - Added a seperate patch to make phy down in deinit part to avoid power > leakage. > - Revert icc bw voting if resume fails(Bjorn Andersson). > - Link to v1: https://lore.kernel.org/r/20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com > > --- > Krishna Chaitanya Chundru (5): > PCI: host-common: Add helper to determine host bridge D3cold eligibility > PCI: dwc: Use common D3cold eligibility helper in suspend path > PCI: qcom: Add .get_ltssm() helper > PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks > PCI: qcom: Add D3cold support > > drivers/pci/controller/dwc/pcie-designware-host.c | 9 +- > drivers/pci/controller/dwc/pcie-qcom.c | 162 +++++++++++++++------- > drivers/pci/controller/pci-host-common.c | 45 ++++++ > drivers/pci/controller/pci-host-common.h | 2 + > 4 files changed, 162 insertions(+), 56 deletions(-) > --- > base-commit: 9702969978695d9a699a1f34771580cdbb153b33 > change-id: 20251229-d3cold-bf99921960bb > > Best regards, With [1] to allow ath12k to go in d3cold: Tested-by: Neil Armstrong # on SM8650-HDK [1] https://lore.kernel.org/all/20260217113142.9140-1-manivannan.sadhasivam@oss.qualcomm.com/