From: David Daney <ddaney@caviumnetworks.com>
To: tglx@linutronix.de, linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org, David Daney <ddaney@caviumnetworks.com>
Subject: [RFC PATCH 0/2] Add IRQ chip hooks for taking CPUs on/off line.
Date: Fri, 18 Mar 2011 14:48:34 -0700 [thread overview]
Message-ID: <1300484916-11133-1-git-send-email-ddaney@caviumnetworks.com> (raw)
When a CPU is brought on-line, per-CPU interrupts need to be enabled
on the new CPU. The local timer and things like perf counters that
rely on interrupts don't work if their interrupts are not enabled.
Likewise when a CPU is taken off-line, we may need to clean up the
interrupts.
I solve both of these problems by adding a pair of function pointers
to the irq_chip structure, along with some simple helper functions to
call them.
When the CPU is being brought on-line, but before interrupts are
enabled, I iterate through all possible IRQs and invoke their
irq_cpu_online() hooks. Most of these are null, so are not called,
but my per-CPU IRQs do have hooks and the corresponding signals are
routed to the new CPU.
There are two patches here.
1) Changes to the core irq code.
2) My SOC/Board interrupt handling rewrite that uses the new
functions.
David Daney (2):
genirq: Add chip hooks for taking CPUs on/off line.
MIPS: Octeon: Rewrite interrupt handling code.
arch/mips/Kconfig | 1 +
arch/mips/cavium-octeon/octeon-irq.c | 1388 ++++++++++++++----------
arch/mips/cavium-octeon/setup.c | 12 -
arch/mips/cavium-octeon/smp.c | 39 +-
arch/mips/include/asm/mach-cavium-octeon/irq.h | 243 ++---
arch/mips/include/asm/octeon/octeon.h | 2 +
arch/mips/pci/msi-octeon.c | 20 +-
include/linux/irq.h | 8 +
include/linux/irqdesc.h | 6 +
kernel/irq/chip.c | 35 +
10 files changed, 968 insertions(+), 786 deletions(-)
--
1.7.2.3
next reply other threads:[~2011-03-18 21:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-18 21:48 David Daney [this message]
2011-03-18 21:48 ` [RFC PATCH 1/2] genirq: Add " David Daney
2011-03-19 20:51 ` Thomas Gleixner
2011-03-21 18:26 ` David Daney
2011-03-21 21:13 ` Thomas Gleixner
2011-03-23 22:03 ` David Daney
2011-03-23 22:09 ` Thomas Gleixner
2011-03-18 21:48 ` [RFC PATCH 2/2] MIPS: Octeon: Rewrite interrupt handling code David Daney
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1300484916-11133-1-git-send-email-ddaney@caviumnetworks.com \
--to=ddaney@caviumnetworks.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®