From: Borislav Petkov <bp@amd64.org>
To: EDAC devel <linux-edac@vger.kernel.org>
Cc: X86-ML <x86@kernel.org>, LKML <linux-kernel@vger.kernel.org>,
Borislav Petkov <borislav.petkov@amd.com>
Subject: [PATCH -v3 6/6] EDAC, MCE, AMD: Add an injector function
Date: Mon, 9 May 2011 20:35:55 +0200 [thread overview]
Message-ID: <1304966155-9841-7-git-send-email-bp@amd64.org> (raw)
In-Reply-To: <1304966155-9841-1-git-send-email-bp@amd64.org>
From: Borislav Petkov <borislav.petkov@amd.com>
Selectively inject either a real MCE or a sw-only version which
exercises the decoding code only. The hardware-injected MCE triggers a
machine check exception (#MC) so that the MCE handler can be bothered to
do something too.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
drivers/edac/mce_amd_inj.c | 50 ++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/edac/mce_amd_inj.c b/drivers/edac/mce_amd_inj.c
index 592871f..45e8122 100644
--- a/drivers/edac/mce_amd_inj.c
+++ b/drivers/edac/mce_amd_inj.c
@@ -131,6 +131,53 @@ static int inj_extcpu_set(void *data, u64 val)
DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");
+static void trigger_mce(void *info)
+{
+ asm volatile("int $18");
+}
+
+static void do_inject(void)
+{
+ u64 mcg_status = 0;
+ unsigned int cpu = i_mce.extcpu;
+ int this_cpu;
+ u8 b = i_mce.bank;
+
+ if (!(i_mce.inject_flags & MCJ_HW_INJECT)) {
+ amd_decode_mce(NULL, 0, &i_mce);
+ return;
+ }
+
+ /* prep MCE global settings for the injection */
+ mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
+
+ if (!(i_mce.status & MCI_STATUS_PCC))
+ mcg_status |= MCG_STATUS_RIPV;
+
+ this_cpu = get_cpu();
+
+ toggle_hw_mce_inject(cpu, true);
+
+ wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
+ (u32)mcg_status, (u32)(mcg_status >> 32));
+
+ wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
+ (u32)i_mce.status, (u32)(i_mce.status >> 32));
+
+ wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
+ (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+
+ wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
+ (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+
+ toggle_hw_mce_inject(cpu, false);
+
+ smp_call_function_single(cpu, trigger_mce, NULL, 0);
+
+ put_cpu();
+
+}
+
/*
* This denotes into which bank we're injecting and triggers
* the injection, at the same time.
@@ -146,8 +193,7 @@ static int inj_bank_set(void *data, u64 val)
}
m->bank = val;
-
- amd_decode_mce(NULL, 0, m);
+ do_inject();
return 0;
}
--
1.7.4.rc2
prev parent reply other threads:[~2011-05-09 18:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-09 18:35 [PATCH -v3 0/6] x86, MCE, AMD: Hardware MCE injection Borislav Petkov
2011-05-09 18:35 ` [PATCH -v3 1/6] x86, MCE: Add a HW injection flag Borislav Petkov
2011-05-10 3:29 ` Hidetoshi Seto
2011-05-10 5:14 ` Borislav Petkov
2011-05-09 18:35 ` [PATCH -v3 2/6] x86, MCE: Export mce_get_debugfs_dir Borislav Petkov
2011-05-09 18:35 ` [PATCH -v3 3/6] EDAC, MCE, AMD: Add function to enable direct write to MCE MSRs Borislav Petkov
2011-05-09 18:35 ` [PATCH -v3 4/6] EDAC, MCE, AMD: Convert to debugfs Borislav Petkov
2011-05-09 18:35 ` [PATCH -v3 5/6] EDAC, MCE, AMD: Add attributes needed for HW injection Borislav Petkov
2011-05-09 18:35 ` Borislav Petkov [this message]
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