From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752134Ab1F3OMd (ORCPT ); Thu, 30 Jun 2011 10:12:33 -0400 Received: from casper.infradead.org ([85.118.1.10]:33955 "EHLO casper.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751097Ab1F3OM2 convert rfc822-to-8bit (ORCPT ); Thu, 30 Jun 2011 10:12:28 -0400 Subject: Re: [PATCH 0/4] perf: Intel uncore pmu counting support From: Peter Zijlstra To: Stephane Eranian Cc: Lin Ming , Ingo Molnar , Andi Kleen , Arnaldo Carvalho de Melo , linux-kernel In-Reply-To: References: <1309421396-17438-1-git-send-email-ming.m.lin@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Date: Thu, 30 Jun 2011 16:10:54 +0200 Message-ID: <1309443054.12449.56.camel@twins> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2011-06-30 at 14:10 +0200, Stephane Eranian wrote: > > This series are cut to support uncore pmu counting only. > > So uncore interrupt handling is not needed. > > > You're making the assumption that when counting, you can never construct > a measurement that will cause a counter to overflow the 39 bits. If not, then > you need interrupt handling even when counting. > Also, I'm missing the stuff that maps everything to one active cpu in the uncore mask. IIRC your previous postings had stuff like that.