From: Suresh Siddha <suresh.b.siddha@intel.com>
To: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
Cc: "x86@kernel.org" <x86@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"hpa@zytor.com" <hpa@zytor.com>, "mingo@elte.hu" <mingo@elte.hu>,
"tglx@linutronix.de" <tglx@linutronix.de>
Subject: Re: [PATCH] x86, x2apic: Preserve high 32-bits of IA32_APIC_BASE MSR
Date: Tue, 12 Jul 2011 10:29:36 -0700 [thread overview]
Message-ID: <1310491776.12417.31.camel@sbsiddha-MOBL3.sc.intel.com> (raw)
In-Reply-To: <20110712055831.2498.78521.sendpatchset@nchumbalkar.americas.cpqcorp.net>
On Mon, 2011-07-11 at 22:59 -0700, Naga Chumbalkar wrote:
> If there's no special reason to zero-out the "high" 32-bits of the IA32_APIC_BASE
> MSR, let's preserve it.
>
> The x2APIC Specification doesn't explicitly state any such requirement. (Sec 2.2
> in: http://www.intel.com/Assets/PDF/manual/318148.pdf).
>
> Signed-off-by: Naga Chumbalkar <nagananda.chumbalkar@hp.com>
> Cc: Suresh Siddha <suresh.b.siddha@intel.com>
>
> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
> index b9338b8..f7b0c7a 100644
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -1429,7 +1429,7 @@ void enable_x2apic(void)
> rdmsr(MSR_IA32_APICBASE, msr, msr2);
> if (!(msr & X2APIC_ENABLE)) {
> printk_once(KERN_INFO "Enabling x2apic\n");
> - wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
> + wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
> }
> }
> #endif /* CONFIG_X86_X2APIC */
yeah, I don't think it was intentional.
Reviewed-by: Suresh Siddha <suresh.b.siddha@intel.com>
next prev parent reply other threads:[~2011-07-12 17:29 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-12 5:59 Naga Chumbalkar
2011-07-12 7:05 ` Cyrill Gorcunov
2011-07-12 17:29 ` Suresh Siddha [this message]
2011-07-12 18:21 ` H. Peter Anvin
2011-07-12 18:36 ` Suresh Siddha
2011-07-12 18:43 ` Chumbalkar, Nagananda
2011-07-13 3:06 ` [tip:x86/apic] " tip-bot for Naga Chumbalkar
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