From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751384Ab1H1MDe (ORCPT ); Sun, 28 Aug 2011 08:03:34 -0400 Received: from mail-ey0-f174.google.com ([209.85.215.174]:36384 "EHLO mail-ey0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750766Ab1H1MDb (ORCPT ); Sun, 28 Aug 2011 08:03:31 -0400 From: Arun Thomas To: Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, Andre Przywara , Fenghua Yu , Christoph Lameter , Tejun Heo , linux-kernel@vger.kernel.org Cc: Arun Thomas Subject: [PATCH] x86, cpu: Add cpufeature flag for TSC-Deadline Date: Sun, 28 Aug 2011 14:03:12 +0200 Message-Id: <1314532992-19495-1-git-send-email-arun.thomas@gmail.com> X-Mailer: git-send-email 1.7.4.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds a flag for TSC-Deadline mode, which allows software to set the local APIC timer to one-shot interrupt at an absolute time (i.e., a TSC deadline). Signed-off-by: Arun Thomas --- arch/x86/include/asm/cpufeature.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index f24ed51..f19e1e8 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -121,6 +121,7 @@ #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ +#define X86_FEATURE_TSC_DEADLINE (4*32+24) /* APIC supports TSC deadline mode */ #define X86_FEATURE_AES (4*32+25) /* AES instructions */ #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ -- 1.7.4.1