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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>,
	vkoul@kernel.org, dmaengine@vger.kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, joy.zou@nxp.com,
	Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH V2] dt-bindings: dma: fsl-edma: Convert to DT schema
Date: Thu, 26 May 2022 14:16:55 +0200	[thread overview]
Message-ID: <1316dd5f-c774-e1c0-892b-7d371936a9eb@linaro.org> (raw)
In-Reply-To: <20220526102438.184803-1-peng.fan@oss.nxp.com>

On 26/05/2022 12:24, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Convert the eDMA controller binding to DT schema.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> 
> V2:
>  Typo fix
>  Correct interrupts/interrupt-names/AllOf
> 
>  .../devicetree/bindings/dma/fsl,edma.yaml     | 140 ++++++++++++++++++
>  .../devicetree/bindings/dma/fsl-edma.txt      | 111 --------------
>  2 files changed, 140 insertions(+), 111 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/dma/fsl,edma.yaml
>  delete mode 100644 Documentation/devicetree/bindings/dma/fsl-edma.txt
> 
> diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> new file mode 100644
> index 000000000000..0a63b0b70f98
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> @@ -0,0 +1,140 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale enhanced Direct Memory Access(eDMA) Controller
> +
> +description: |
> +  The eDMA channels have multiplex capability by programmable
> +  memory-mapped registers. channels are split into two groups, called
> +  DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
> +  by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
> +
> +maintainers:
> +  - Peng Fan <peng.fan@nxp.com>
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - enum:
> +          - fsl,vf610-edma
> +          - fsl,imx7ulp-edma
> +      - items:
> +          - const: fsl,ls1028a-edma
> +          - const: fsl,vf610-edma
> +

The reg and interrupts should still be there (matching the widest of
constraints).

> +  "#dma-cells":
> +    const: 2
> +
> +  dma-channels:
> +    const: 32
> +
> +  clocks:
> +    maxItems: 2

Also clock-names with maxItems:2

> +
> +  big-endian:
> +    description: |
> +      If present registers and hardware scatter/gather descriptors of the
> +      eDMA are implemented in big endian mode, otherwise in little mode.
> +    type: boolean
> +

Best regards,
Krzysztof

      reply	other threads:[~2022-05-26 12:17 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-26 10:24 Peng Fan (OSS)
2022-05-26 12:16 ` Krzysztof Kozlowski [this message]

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