From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8B1AC6FA92 for ; Wed, 21 Sep 2022 10:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbiIUKKv (ORCPT ); Wed, 21 Sep 2022 06:10:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230393AbiIUKKN (ORCPT ); Wed, 21 Sep 2022 06:10:13 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50E2B5A835 for ; Wed, 21 Sep 2022 03:10:12 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id w8so8307265lft.12 for ; Wed, 21 Sep 2022 03:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date; bh=yxhsCHqbjeaUvDSrWwmS/tUjVYbJlbwwcVnNivmxf/A=; b=Mx7+v7mLDXYL9fZJN81ZLtHPaaRSjT+E201/j9MMBacZSRokSKMoitW9Kj6QZeFCfc 5KgqLjmvBVDHm1PQr2blWlEPWQY8I2wreEH0ThGty+Nm1LpGMQbSVt0jjd0+8V+fxWbc aZHdCVM+JrKPXIITHE2oz24+bHztTA+QVFxyZcAIgUNZYqopCE77QX1aPYlqWv3hiYpv s6hx4P8rHUxBqsam0PFddMEK0cEizIyZuv2ztE/pD8vHs7UDYAWJ714lt8GIgLdXoSpy lhxbCCMCjWQAe+yapph8KF6kewtaIxLyW4qJ63h3LZp1MUOmFT3n1RquYE03323Qkbsc THQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date; bh=yxhsCHqbjeaUvDSrWwmS/tUjVYbJlbwwcVnNivmxf/A=; b=I6qlipOntYeEOg9oZXrH/NmUkbB1M2XmEM847KXzQT+hAVK0GqiKifgbbCeIi9wq+T jDy3QDfOeAVnSueWywsa6frDARLoHZ1/FRd+76maAyOrVAux7Qg7kKtZJ1dAvbKmdTae HL6fG0hMxRr/XS+oSlvPGFmt54+dNLq/TITKZHkOJxbXrkdiGod7xgAOPSzrgcHDtG9c ldTVWRYwHwQKIIJRrkQ0jU657I8I60bhtQ6okpnCeMu/unnzV4SW1BXBq6yPnUIKte3h xVC1TsBpqt5e11Ywejf7v1F5t6UeNWOY+CXx4Fwm11VNPPajo21qGwG4h2PaSv9nmOd0 Jgbg== X-Gm-Message-State: ACrzQf2TqggMnUQONKdIXp9MzwMtdEQKxabKV2s2Z6eRJhIHIZzv4Bc8 oAaZ9PsNeYauxFWPy+W0I9u5AA== X-Google-Smtp-Source: AMsMyM7miLYxhwhmdAm6xqnhxaOOx6BmPBe4KQD2NDEVZSgjClHYYwttY/drvejnXcRy+vqeDU5rVg== X-Received: by 2002:a05:6512:68a:b0:49f:4c31:e9f with SMTP id t10-20020a056512068a00b0049f4c310e9fmr10129696lfe.136.1663755010574; Wed, 21 Sep 2022 03:10:10 -0700 (PDT) Received: from [192.168.0.21] (78-11-189-27.static.ip.netia.com.pl. [78.11.189.27]) by smtp.gmail.com with ESMTPSA id o12-20020a056512052c00b00497a41b3a42sm370469lfc.88.2022.09.21.03.10.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Sep 2022 03:10:09 -0700 (PDT) Message-ID: <131d9058-a9de-7012-49e0-95e8477edf85@linaro.org> Date: Wed, 21 Sep 2022 12:10:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: Similar SoCs with different CPUs and interrupt bindings Content-Language: en-US To: Geert Uytterhoeven Cc: "Lad, Prabhakar" , Rob Herring , Krzysztof Kozlowski , Andre Przywara , Conor Dooley , Samuel Holland , Biju Das , Chris Paterson , Atish Patra , "Lad, Prabhakar" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-riscv , Linux ARM , Linux-Renesas , Linux Kernel Mailing List , Arnd Bergmann , Olof Johansson References: From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/09/2022 12:08, Geert Uytterhoeven wrote: >> diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi >> index ff6aab388eb7..0ecca775fa3f 100644 >> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi >> @@ -8,6 +8,8 @@ >> #include >> #include >> >> +#define SOC_PERIPHERAL_IRQ_NUMBER(na) (na + 32) >> +#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr SOC_PERIPHERAL_IRQ_NUMBER(na) > > #define SOC_PERIPHERAL_IRQ(nr, flags) GIC_SPI > SOC_PERIPHERAL_IRQ_NUMBER(nr) flags Right. Let's consider my code just proof-of-concept :) Best regards, Krzysztof