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September 2026, 07:47:58 Mitteleurop=C3=A4ische Normalzei= t schrieb Aristo Chen: > The HDMI PHY clock reports 74.25 MHz when cur_cfg is unset, but does > not establish that rate in hardware. The common clock framework caches > the reported rate when registering the clock and skips a first > clk_set_rate(74250000) request because the rate appears unchanged. >=20 > Consequently, a display whose initial mode uses a 74.25 MHz pixel clock > can leave the PHY with its bootloader register state and receive no > TMDS signal. Requesting another rate first avoids the issue because the > set_rate callback configures the PHY. >=20 > Program the 74.25 MHz table entry with the reference clock enabled > before registering the clock provider. recalc_rate can then report the > configured rate, and a skipped first rate change is safe. Also enable > the reference clock when restoring that configuration on resume. >=20 > Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY") > Signed-off-by: Aristo Chen Unfortunately this breaks my platform (imx8mp-tqma8mpql-mba8mpxl.dts). With this patch applied I get the following errors in kernel log: > fsl-samsung-hdmi-phy 32fdff00.phy: PLL failed to lock > fsl-samsung-hdmi-phy 32fdff00.phy: error -ETIMEDOUT: failed to configure = default rate > fsl-samsung-hdmi-phy 32fdff00.phy: probe with driver fsl-samsung-hdmi-phy= failed with error -110 Reverting fixes my platform and HDMI as expected. Best regards, Alexander > --- > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 59 +++++++++++++++----- > 1 file changed, 44 insertions(+), 15 deletions(-) >=20 > diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/f= reescale/phy-fsl-samsung-hdmi.c > index 0f25d81de61b..41addd4ad414 100644 > --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > @@ -44,6 +44,8 @@ > #define MHZ (1000UL * 1000UL) > #endif > =20 > +#define PHY_DEFAULT_RATE 74250000 > + > #define PHY_PLL_DIV_REGS_NUM 7 > =20 > struct phy_config { > @@ -489,17 +491,6 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl= _samsung_hdmi_phy *phy, > return ret; > } > =20 > -static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, > - unsigned long parent_rate) > -{ > - struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); > - > - if (!phy->cur_cfg) > - return 74250000; > - > - return phy->cur_cfg->pixclk; > -} > - > /* Helper function to lookup the available fractional-divider rate */ > static const struct phy_config *fsl_samsung_hdmi_phy_lookup_rate(unsigne= d long rate) > { > @@ -520,6 +511,14 @@ static const struct phy_config *fsl_samsung_hdmi_phy= _lookup_rate(unsigned long r > &phy_pll_cfg[i] : &phy_pll_cfg[i+1]); > } > =20 > +static unsigned long phy_clk_recalc_rate(struct clk_hw *hw, > + unsigned long parent_rate) > +{ > + struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); > + > + return phy->cur_cfg->pixclk; > +} > + > static void fsl_samsung_hdmi_calculate_phy(struct phy_config *cal_phy, u= nsigned long rate, > u8 p, u16 m, u8 s) > { > @@ -640,6 +639,7 @@ static int phy_clk_register(struct fsl_samsung_hdmi_p= hy *phy) > =20 > static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev) > { > + const struct phy_config *default_cfg; > struct fsl_samsung_hdmi_phy *phy; > int ret; > =20 > @@ -664,6 +664,23 @@ static int fsl_samsung_hdmi_phy_probe(struct platfor= m_device *pdev) > return dev_err_probe(phy->dev, PTR_ERR(phy->refclk), > "failed to get ref clk\n"); > =20 > + /* > + * Establish the rate reported by recalc_rate() before registering the > + * clock. Otherwise CCF may skip the first set_rate() when it requests > + * the assumed default rate, leaving the PHY unconfigured. > + */ > + ret =3D clk_prepare_enable(phy->refclk); > + if (ret) > + return dev_err_probe(phy->dev, ret, > + "failed to enable ref clk\n"); > + > + default_cfg =3D fsl_samsung_hdmi_phy_lookup_rate(PHY_DEFAULT_RATE); > + ret =3D fsl_samsung_hdmi_phy_configure(phy, default_cfg); > + clk_disable_unprepare(phy->refclk); > + if (ret) > + return dev_err_probe(phy->dev, ret, > + "failed to configure default rate\n"); > + > pm_runtime_get_noresume(phy->dev); > pm_runtime_set_active(phy->dev); > pm_runtime_enable(phy->dev); > @@ -702,7 +719,7 @@ static int __maybe_unused fsl_samsung_hdmi_phy_suspen= d(struct device *dev) > static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev) > { > struct fsl_samsung_hdmi_phy *phy =3D dev_get_drvdata(dev); > - int ret =3D 0; > + int ret; > =20 > ret =3D clk_prepare_enable(phy->apbclk); > if (ret) { > @@ -710,11 +727,23 @@ static int __maybe_unused fsl_samsung_hdmi_phy_resu= me(struct device *dev) > return ret; > } > =20 > - if (phy->cur_cfg) > - ret =3D fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); > + if (!phy->cur_cfg) > + return 0; > =20 > - return ret; > + ret =3D clk_prepare_enable(phy->refclk); > + if (ret) { > + dev_err(phy->dev, "failed to enable ref clk\n"); > + goto disable_apbclk; > + } > + > + ret =3D fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg); > + clk_disable_unprepare(phy->refclk); > + if (!ret) > + return 0; > =20 > +disable_apbclk: > + clk_disable_unprepare(phy->apbclk); > + return ret; > } > =20 > static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops, >=20 =2D-=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider http://www.tq-group.com/