From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758763Ab2BJAHu (ORCPT ); Thu, 9 Feb 2012 19:07:50 -0500 Received: from mx1.redhat.com ([209.132.183.28]:1876 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758658Ab2BJABh (ORCPT ); Thu, 9 Feb 2012 19:01:37 -0500 From: Mauro Carvalho Chehab Cc: Mauro Carvalho Chehab , Linux Edac Mailing List , Linux Kernel Mailing List Subject: [PATCH v3 08/31] edac: Better describe the memory concepts The memory terms changed along the time, since when EDAC were originally written: new concepts were introduced, and some things have different meanings, depending on the memory architecture. Better define those terms, and better describe each supported memory type. Date: Thu, 9 Feb 2012 22:01:07 -0200 Message-Id: <1328832090-9166-9-git-send-email-mchehab@redhat.com> In-Reply-To: <1328832090-9166-1-git-send-email-mchehab@redhat.com> References: <1328832090-9166-1-git-send-email-mchehab@redhat.com> To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional changes. Just comments were touched. Signed-off-by: Mauro Carvalho Chehab --- include/linux/edac.h | 176 ++++++++++++++++++++++++++++++++++++++------------ 1 files changed, 134 insertions(+), 42 deletions(-) diff --git a/include/linux/edac.h b/include/linux/edac.h index 027e478..0f700e3 100644 --- a/include/linux/edac.h +++ b/include/linux/edac.h @@ -72,25 +72,91 @@ enum hw_event_mc_err_type { HW_EVENT_ERR_FATAL, }; -/* memory types */ +/** + * enum mem_type - memory types + * + * @MEM_EMPTY Empty csrow + * @MEM_RESERVED: Reserved csrow type + * @MEM_UNKNOWN: Unknown csrow type + * @MEM_FPM: Fast page mode + * An old asyncronous memory technology, encapsulated as + * SIMM, popularly used between 1987-1995. + * @MEM_EDO: Extended data out + * Asynchronous memory technology used on early Pentium's + * (1995-1998). + * @MEM_BEDO: Burst Extended data out + * EDO memories with performance improvement gains. + * @MEM_SDR: Single data rate SDRAM + * First types of syncronous ram specified by JEDEC + * popular between 1998-2002. The JEDEC standards defined + * 3 types of sticks: PC66, PC100 and PC133. There were + * also some non-official overclocked sticks like PC150 + * and PC166. + * There are 3 pins for chip select: Pins 0 and 2 are + * for rank 0; pins 1 and 3 are for rank 1, if the memory + * is dual-rank. + * @MEM_RDR: Registered single data rate SDRAM + * @MEM_DDR: Double data rate SDRAM, used between 2002 and 2005. + * The JEDEC standards defined sticks PC1600, PC2100, + * PC2700 and PC3200. Non-official overclocked sticks + * also exists. + * On DDR memories, there are one or two channels. A + * single-channel mode means that one x72 ECC dimm is + * accessed, in order to provide 64 bits of data. On + * dual-channel mode, two dimm's are used simultaneously, + * in order to provide a 128 bits of data. The "cschannel" + * concept used on EDAC refers to such channel type. + * @MEM_RDDR: Registered Double data rate SDRAM + * This is a variant of the DDR memories. + * A registered memory has a buffer inside it, hiding + * part of the memory details to the memory controller. + * @MEM_RMBS: Rambus DRAM + * Rambus uses a high-speed multi-drop serial bus to + * communicate with each RDRAM chip, used on some + * machines between 2000-2002 (Pentium III and IV). + * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F. + * Those memories are labed as "PC2-" instead of "PC" to + * differenciate from DDR. + * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205 + * and JESD206. + * A FB-DIMM channel consists of 14 unidirectional signal + * pairs (Northbound path) from the memories to the MC + * and 10 unidirectional signal pairs (Southbond path) + * from the MC to the DIMM's. + * those memories are x72 ECC DIMMs. Up to 8 DIMMs can + * be connected per channel. When used with 128 bits, + * two channels are needed. The grouping of those two + * channels is called "branch". + * @MEM_RDDR2: Registered DDR2 RAM + * This is a variant of the DDR2 memories. + * @MEM_XDR: Rambus XDR + * It is an evolution of the original RAMBUS memories, + * created to compete with DDR2. Weren't used on any + * x86 arch, but cell_edac PPC memory controller uses it. + * @MEM_DDR3: DDR3 RAM + * Those memories are labed as "PC3-" to differenciate + * from DDR and DDR2. + * @MEM_RDDR3: Registered DDR3 RAM + * This is a variant of the DDR3 memories. + */ enum mem_type { - MEM_EMPTY = 0, /* Empty csrow */ - MEM_RESERVED, /* Reserved csrow type */ - MEM_UNKNOWN, /* Unknown csrow type */ - MEM_FPM, /* Fast page mode */ - MEM_EDO, /* Extended data out */ - MEM_BEDO, /* Burst Extended data out */ - MEM_SDR, /* Single data rate SDRAM */ - MEM_RDR, /* Registered single data rate SDRAM */ - MEM_DDR, /* Double data rate SDRAM */ - MEM_RDDR, /* Registered Double data rate SDRAM */ - MEM_RMBS, /* Rambus DRAM */ - MEM_DDR2, /* DDR2 RAM */ - MEM_FB_DDR2, /* fully buffered DDR2 */ - MEM_RDDR2, /* Registered DDR2 RAM */ - MEM_XDR, /* Rambus XDR */ - MEM_DDR3, /* DDR3 RAM */ - MEM_RDDR3, /* Registered DDR3 RAM */ + MEM_EMPTY = 0, + MEM_RESERVED, + MEM_UNKNOWN, + MEM_FPM, + MEM_EDO, + MEM_BEDO, + MEM_SDR, + MEM_RDR, + MEM_DDR, + MEM_RDDR, + MEM_RMBS, + MEM_DDR2, + MEM_FB_DDR2, + MEM_RDDR2, + MEM_XDR, + MEM_DDR3, + MEM_RDDR3, }; #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) @@ -168,8 +234,9 @@ enum scrub_type { #define OP_OFFLINE 0x300 /* - * There are several things to be aware of that aren't at all obvious: + * Concepts used at the EDAC subsystem * + * There are several things to be aware of that aren't at all obvious: * * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. * @@ -178,36 +245,61 @@ enum scrub_type { * creating a common ground for discussion, terms and their definitions * will be established. * - * Memory devices: The individual chip on a memory stick. These devices - * commonly output 4 and 8 bits each. Grouping several - * of these in parallel provides 64 bits which is common - * for a memory stick. + * Memory devices: The individual DRAM chips on a memory stick. These + * devices commonly output 4 and 8 bits each (x4, x8). + * Grouping several of these in parallel provides the + * number of bits that the memory controller expects: + * typically 72 bits, in order to provide 64 bits of ECC + * corrected data. * * Memory Stick: A printed circuit board that aggregates multiple - * memory devices in parallel. This is the atomic - * memory component that is purchaseable by Joe consumer - * and loaded into a memory socket. + * memory devices in parallel. In general, this is the + * First replaceable unit (FRU) that the final consumer + * cares to replace. It is typically encapsulated as DIMMs * * Socket: A physical connector on the motherboard that accepts * a single memory stick. * - * Csrow-channel: Set of memory devices on a memory stick that must be - * grouped in parallel with one or more additional - * channels from other memory sticks. This parallel - * grouping of the output from multiple channels are - * necessary for the smallest granularity of memory access. - * Some memory controllers are capable of single channel - - * which means that memory sticks can be loaded - * individually. Other memory controllers are only - * capable of dual channel - which means that memory - * sticks must be loaded as pairs (see "socket set"). + * Branch: The highest hierarchy on a Fully-Buffered DIMM memory + * controller. Typically, it contains two channels. + * Two channels at the same branch can be used in single + * mode or in lockstep mode. + * When lockstep is enabled, the cache line is higher, + * but it generally brings some performance penalty. + * Also, it is generally not possible to point to just one + * memory stick when an error occurs, as the error + * correction code is calculated using two dimms instead + * of one. Due to that, it is capable of correcting more + * errors than on single mode. + * + * Channel: A memory controller channel, responsible to communicate + * with a group of DIMM's. Each channel has its own + * independent control (command) and data bus, and can + * be used independently or grouped. + * + * Single-channel: The data accessed by the memory controller is contained + * into one dimm only. E. g. if the data is 64 bits-wide, + * the data flows to the CPU using one 64 bits parallel + * access. + * Typically used with SDR, DDR, DDR2 and DDR3 memories. + * FB-DIMM and RAMBUS use a different concept for channel, + * so this concept doesn't apply there. + * + * Double-channel: The data size accessed by the memory controller is + * contained into two dimms accessed at the same time. + * E. g. if the DIMM is 64 bits-wide, the data flows to + * the CPU using a 128 bits parallel access. + * Typically used with SDR, DDR, DDR2 and DDR3 memories. + * FB-DIMM and RAMBUS uses a different concept for channel, + * so this concept doesn't apply there. * - * Chip-select row: All of the memory devices that are selected together. - * for a single, minimum grain of memory access. - * This selects all of the parallel memory devices across - * all of the parallel channels. Common chip-select rows - * for single channel are 64 bits, for dual channel 128 - * bits. + * Chip-select row: This is the name of the memory controller signal used + * to select the DRAM chips to be used. It may not be + * visible by the memory controller, as some memory buffer + * chip may be responsible to control it. + * On devices where it is visible, it controls the DIMM + * (or the DIMM pair, in dual-channel mode) that is + * accessed by the memory controller. * * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory. * Motherboards commonly drive two chip-select pins to -- 1.7.8