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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000397AE.mail.protection.outlook.com (10.167.248.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7828.19 via Frontend Transport; Mon, 29 Jul 2024 09:13:40 +0000 Received: from [10.136.40.92] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 29 Jul 2024 04:13:33 -0500 Message-ID: <132ddbbd-5afc-8436-9db6-0f1add4bcec1@amd.com> Date: Mon, 29 Jul 2024 14:43:31 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH] perf/x86: Fix smp_processor_id()-in-preemptible warnings Content-Language: en-US To: Li Huafei , , , CC: , , , , , , , , , , , , , , References: <20240729114541.3517574-1-lihuafei1@huawei.com> From: K Prateek Nayak In-Reply-To: <20240729114541.3517574-1-lihuafei1@huawei.com> Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2024 09:13:40.0084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fce7c3fc-c580-4350-308f-08dcafaebc77 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8280 Hello Huafei, On 7/29/2024 5:15 PM, Li Huafei wrote: > The following bug was triggered on a system built with > CONFIG_DEBUG_PREEMPT=y: > > # echo p > /proc/sysrq-trigger > > BUG: using smp_processor_id() in preemptible [00000000] code: sh/117 > caller is perf_event_print_debug+0x1a/0x4c0 > CPU: 3 UID: 0 PID: 117 Comm: sh Not tainted 6.11.0-rc1 #109 > Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1ubuntu1.1 04/01/2014 > Call Trace: > > dump_stack_lvl+0x4f/0x60 > check_preemption_disabled+0xc8/0xd0 > perf_event_print_debug+0x1a/0x4c0 > __handle_sysrq+0x140/0x180 > write_sysrq_trigger+0x61/0x70 > proc_reg_write+0x4e/0x70 > vfs_write+0xd0/0x430 > ? handle_mm_fault+0xc8/0x240 > ksys_write+0x9c/0xd0 > do_syscall_64+0x96/0x190 > entry_SYSCALL_64_after_hwframe+0x4b/0x53 > > This is because the commit d4b294bf84db ("perf/x86: Hybrid PMU support > for counters") took smp_processor_id() outside the irq critical section. > If a preemption occurs in perf_event_print_debug() and the task is > migrated to another cpu, we may get incorrect pmu debug information. > Move smp_processor_id() back inside the irq critical section to fix this > issue. > > Fixes: d4b294bf84db ("perf/x86: Hybrid PMU support for counters") > Signed-off-by: Li Huafei > --- > arch/x86/events/core.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 12f2a0c14d33..c0157a5d8296 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -1521,19 +1521,24 @@ void perf_event_print_debug(void) > { > u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; > u64 pebs, debugctl; > - int cpu = smp_processor_id(); > - struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); > - unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); > - unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); > - struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); > + int cpu; > + struct cpu_hw_events *cpuc; > + unsigned long *cntr_mask, *fixed_cntr_mask; > + struct event_constraint *pebs_constraints; > unsigned long flags; > int idx; nit. "cpu" and "idx" can be defined together and this can be converted to use revere xmas tree order. > > + local_irq_save(flags); Perhaps use "guard(irqsave)();" here since ... > + > + cpu = smp_processor_id(); > + cpuc = &per_cpu(cpu_hw_events, cpu); > + cntr_mask = hybrid(cpuc->pmu, cntr_mask); > + fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); > + pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); > + > if (!*(u64 *)cntr_mask) ... a "local_irq_restore(flags)" is required here now before returning and using the guard can avoid that. Even the flags variable will no longer be necessary. Thoughts? > return; > > - local_irq_save(flags); > - > if (x86_pmu.version >= 2) { > rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); > rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); -- Thanks and Regards, Prateek