From: Alex Shi <alex.shi@intel.com>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
arnd@arndb.de, rostedt@goodmis.org, fweisbec@gmail.com
Cc: jeremy@goop.org, riel@redhat.com, luto@mit.edu,
alex.shi@intel.com, avi@redhat.com, len.brown@intel.com,
dhowells@redhat.com, fenghua.yu@intel.com,
borislav.petkov@amd.com, yinghai@kernel.org, ak@linux.intel.com,
cpw@sgi.com, steiner@sgi.com, akpm@linux-foundation.org,
penberg@kernel.org, hughd@google.com, rientjes@google.com,
kosaki.motohiro@jp.fujitsu.com, n-horiguchi@ah.jp.nec.com,
tj@kernel.org, oleg@redhat.com, axboe@kernel.dk,
jmorris@namei.org, a.p.zijlstra@chello.nl,
kamezawa.hiroyu@jp.fujitsu.com, viro@zeniv.linux.org.uk,
linux-kernel@vger.kernel.org, yongjie.ren@intel.com
Subject: [PATCH v5 7/7] x86/tlb: add tlb_flushall_shift knob into debugfs
Date: Tue, 15 May 2012 16:55:38 +0800 [thread overview]
Message-ID: <1337072138-8323-8-git-send-email-alex.shi@intel.com> (raw)
In-Reply-To: <1337072138-8323-1-git-send-email-alex.shi@intel.com>
kernel will replace cr3 rewrite with invlpg when
tlb_flush_entries <= active_tlb_entries / 2^tlb_flushall_factor
if tlb_flushall_factor is -1, kernel won't do this replacement.
User can modify its value according to specific CPU/applications.
Thanks for Borislav providing the help message of
CONFIG_DEBUG_TLBFLUSH.
Signed-off-by: Alex Shi <alex.shi@intel.com>
---
arch/x86/Kconfig.debug | 19 +++++++++++++++++++
arch/x86/mm/tlb.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index e46c214..b322f12 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -129,6 +129,25 @@ config DOUBLEFAULT
option saves about 4k and might cause you much additional grey
hair.
+config DEBUG_TLBFLUSH
+ bool "Set upper limit of TLB entries to flush one-by-one"
+ depends on DEBUG_KERNEL && (X86_64 || X86_INVLPG)
+ ---help---
+
+ X86-only for now.
+
+ This option allows the user to tune the amount of TLB entries the
+ kernel flushes one-by-one instead of doing a full TLB flush. In
+ certain situations, the former is cheaper. This is controlled by the
+ tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it
+ to -1, the code flushes the whole TLB unconditionally. Otherwise,
+ for positive values of it, the kernel will use single TLB entry
+ invalidating instructions according to the following formula:
+
+ flush_entries <= active_tlb_entries / 2^tlb_flushall_shift
+
+ If in doubt, say "N".
+
config IOMMU_DEBUG
bool "Enable IOMMU debugging"
depends on GART_IOMMU && DEBUG_KERNEL
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index b2e25e8..b77c764 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -12,6 +12,7 @@
#include <asm/cache.h>
#include <asm/apic.h>
#include <asm/uv/uv.h>
+#include <linux/debugfs.h>
DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
= { &init_mm, 0, };
@@ -429,3 +430,50 @@ void flush_tlb_all(void)
{
on_each_cpu(do_flush_tlb_all, NULL, 1);
}
+
+#ifdef CONFIG_DEBUG_TLBFLUSH
+static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ char buf[32];
+ unsigned int len;
+
+ len = sprintf(buf, "%hd\n", tlb_flushall_shift);
+ return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static ssize_t tlbflush_write_file(struct file *file,
+ const char __user *user_buf, size_t count, loff_t *ppos)
+{
+ char buf[32];
+ ssize_t len;
+ u16 shift;
+
+ len = min(count, sizeof(buf) - 1);
+ if (copy_from_user(buf, user_buf, len))
+ return -EFAULT;
+
+ buf[len] = '\0';
+ if (kstrtos16(buf, 0, &shift))
+ return -EINVAL;
+
+ tlb_flushall_shift = shift;
+ return count;
+}
+
+static const struct file_operations fops_tlbflush = {
+ .read = tlbflush_read_file,
+ .write = tlbflush_write_file,
+ .llseek = default_llseek,
+};
+
+static int __cpuinit create_tlb_flushall_shift(void)
+{
+ if (cpu_has_invlpg) {
+ debugfs_create_file("tlb_flushall_shift", S_IRUSR | S_IWUSR,
+ arch_debugfs_dir, NULL, &fops_tlbflush);
+ }
+ return 0;
+}
+late_initcall(create_tlb_flushall_shift);
+#endif
--
1.7.5.4
prev parent reply other threads:[~2012-05-15 8:57 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-15 8:55 [PATCH v5 0/7] tlb flush optimization for x86 Alex Shi
2012-05-15 8:55 ` [PATCH v5 1/7] x86/tlb: unify TLB_FLUSH_ALL definition Alex Shi
2012-05-15 8:55 ` [PATCH v5 2/7] x86/tlb_info: get last level TLB entry number of CPU Alex Shi
2012-05-15 8:55 ` [PATCH v5 3/7] x86/flush_tlb: try flush_tlb_single one by one in flush_tlb_range Alex Shi
2012-05-15 8:55 ` [PATCH v5 4/7] x86/tlb: fall back to flush all when meet a THP large page Alex Shi
2012-05-15 8:55 ` [PATCH v5 5/7] x86/tlb: add tlb_flushall_shift for specific CPU Alex Shi
2012-05-16 6:49 ` Alex Shi
2012-05-16 17:55 ` H. Peter Anvin
2012-05-17 1:46 ` Alex Shi
2012-05-15 8:55 ` [PATCH v5 6/7] x86/tlb: optimizing flush_tlb_mm Alex Shi
2012-05-15 9:11 ` Peter Zijlstra
2012-05-15 9:15 ` Nick Piggin
2012-05-15 9:17 ` Nick Piggin
2012-05-15 12:58 ` Luming Yu
2012-05-15 13:06 ` Peter Zijlstra
2012-05-15 13:27 ` Luming Yu
2012-05-15 13:28 ` Alex Shi
2012-05-15 13:33 ` Alex Shi
2012-05-15 13:39 ` Steven Rostedt
2012-05-15 14:04 ` Borislav Petkov
2012-05-15 13:08 ` Luming Yu
2012-05-15 14:07 ` Alex Shi
2012-05-15 9:18 ` Peter Zijlstra
2012-05-15 9:52 ` Nick Piggin
2012-05-15 10:00 ` Peter Zijlstra
2012-05-15 10:06 ` Nick Piggin
2012-05-15 10:13 ` Peter Zijlstra
2012-05-15 14:04 ` Alex Shi
2012-05-15 13:24 ` Alex Shi
2012-05-15 14:36 ` Peter Zijlstra
2012-05-15 14:57 ` Peter Zijlstra
2012-05-15 15:01 ` Alex Shi
2012-05-16 6:46 ` Alex Shi
2012-05-16 8:00 ` Peter Zijlstra
2012-05-16 8:04 ` Peter Zijlstra
2012-05-16 8:53 ` Alex Shi
2012-05-16 8:58 ` Peter Zijlstra
2012-05-16 10:58 ` Alex Shi
2012-05-16 11:04 ` Peter Zijlstra
2012-05-16 12:57 ` Alex Shi
2012-05-16 13:34 ` Alex Shi
2012-05-16 21:09 ` Peter Zijlstra
2012-05-17 0:43 ` Alex Shi
2012-05-17 2:07 ` Steven Rostedt
2012-05-17 8:04 ` Alex Shi
2012-05-17 2:14 ` Paul Mundt
2012-05-16 13:44 ` Alex Shi
2012-05-15 8:55 ` Alex Shi [this message]
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