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Subject: Re: [PATCH v5 6/7] x86/tlb: optimizing flush_tlb_mm
From: Steven Rostedt <rostedt@goodmis.org>
To: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Luming Yu <luming.yu@gmail.com>, Nick Piggin <npiggin@gmail.com>,
        Alex Shi <alex.shi@intel.com>, tglx@linutronix.de, mingo@redhat.com,
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Date: Tue, 15 May 2012 09:39:05 -0400
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On Tue, 2012-05-15 at 15:06 +0200, Peter Zijlstra wrote:
> On Tue, 2012-05-15 at 20:58 +0800, Luming Yu wrote:
> > 
> > 
> > Both __native_flush_tlb() and __native_flush_tlb_single(...)
> > introduced roughly 1 ns  latency to tsc sampling executed in
> > stop_machine_context in two logical CPUs 
> 
> But you have to weight that against the cost of re-population, and
> that's the difficult bit, since we have no clue how many tlb entries are
> in use by the current cr3.
> 
> It might be possible for intel to give us this information, I've asked
> for something similar for cachelines.

What information? The # of tlb entries in use?

-- Steve