From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752161Ab2FLJJY (ORCPT ); Tue, 12 Jun 2012 05:09:24 -0400 Received: from mga01.intel.com ([192.55.52.88]:22878 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750876Ab2FLJJX (ORCPT ); Tue, 12 Jun 2012 05:09:23 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="178775517" From: Alex Shi To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, arnd@arndb.de, rostedt@goodmis.org, fweisbec@gmail.com Cc: jeremy@goop.org, seto.hidetoshi@jp.fujitsu.com, borislav.petkov@amd.com, alex.shi@intel.com, tony.luck@intel.com, luto@mit.edu, riel@redhat.com, avi@redhat.com, len.brown@intel.com, tj@kernel.org, akpm@linux-foundation.org, cl@gentwo.org, ak@linux.intel.com, jbeulich@suse.com, eric.dumazet@gmail.com, akinobu.mita@gmail.com, cpw@sgi.com, penberg@kernel.org, steiner@sgi.com, viro@zeniv.linux.org.uk, kamezawa.hiroyu@jp.fujitsu.com, aarcange@redhat.com, rientjes@google.com, linux-kernel@vger.kernel.org Subject: [PATCH v8 0/8] x86 TLB flush range optimizing Date: Tue, 12 Jun 2012 17:06:37 +0800 Message-Id: <1339492005-20241-1-git-send-email-alex.shi@intel.com> X-Mailer: git-send-email 1.7.5.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This version patches rebases on 3.5-rc2 kernel. It does some code clean up, change patches sequency to make it looks more logical. It also includes xen code change according to Jan Beulich's comments, includes comments update of tlb flushing IPI according to PeterZ's suggestions. And Adding the flush_tlb_kernel_range support by invlpg. Thanks for all comments! and appreciate for more. :) Alex Shi [PATCH v8 1/8] x86/tlb_info: get last level TLB entry number of CPU [PATCH v8 2/8] x86/flush_tlb: try flush_tlb_single one by one in [PATCH v8 3/8] x86/tlb: fall back to flush all when meet a THP large [PATCH v8 4/8] x86/tlb: add tlb_flushall_shift for specific CPU [PATCH v8 5/8] x86/tlb: add tlb_flushall_shift knob into debugfs [PATCH v8 6/8] x86/tlb: enable tlb flush range support for generic [PATCH v8 7/8] x86/tlb: replace INVALIDATE_TLB_VECTOR by [PATCH v8 8/8] x86/tlb: do flush_tlb_kernel_range by 'invlpg'