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Subject: Re: [PATCH] select GENERIC_ATOMIC64 for c6x/score/unicore32 archs
From: Mark Salter <msalter@redhat.com>
To: Fengguang Wu <fengguang.wu@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>,
        "Eric W. Biederman" <ebiederm@xmission.com>,
        linux-kernel@vger.kernel.org, Aurelien Jacquiot <a-jacquiot@ti.com>,
        linux-c6x-dev@linux-c6x.org, Lennox Wu <lennox.wu@gmail.com>,
        Guan Xuetao <gxt@mprc.pku.edu.cn>
Date: Wed, 15 Aug 2012 09:42:58 -0400
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On Wed, 2012-08-15 at 10:36 +0800, Fengguang Wu wrote:
> > -#define L1_CACHE_BYTES        L2_CACHE_BYTES
> > +#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
> > +#define L1_CACHE_BYTES        (1 << L2_CACHE_SHIFT)
> 
> Nitpick: the last line could better be:
> 
> +#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
> 
> Reviewed-by: Fengguang Wu <fengguang.wu@intel.com>

Yes, I noticed that after sending the patch.

Should I push this through the c6x tree?

--Mark