From: Suresh Siddha <suresh.b.siddha@intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: mingo@elte.hu, tglx@linutronix.de, hpa@zytor.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/4] x86: xor-block handling adjustments
Date: Mon, 10 Sep 2012 12:20:37 -0700 [thread overview]
Message-ID: <1347304838.26695.99.camel@sbsiddha-desk.sc.intel.com> (raw)
In-Reply-To: <504DFB10020000780009A321@nat28.tlf.novell.com>
On Mon, 2012-09-10 at 13:37 +0100, Jan Beulich wrote:
> 1: unify SSE-base xor-block routines
> 2: improve XMM register spill/fill
> 3: add alternative SSE implementation only prefetching once per 64-byte line
> 4: make virtualization friendly
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Jan, There are some relevant changes in tip/x86/fpu branch. Can you
please build your patches on top of that?
thanks,
suresh
next prev parent reply other threads:[~2012-09-10 19:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-10 12:37 Jan Beulich
2012-09-10 19:20 ` Suresh Siddha [this message]
2012-09-21 15:28 ` Jan Beulich
2012-09-21 16:11 ` H. Peter Anvin
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