From: Jim Lin <jilin@nvidia.com>
To: <gregkh@linuxfoundation.org>, <swarren@wwwdotorg.org>
Cc: <linux-usb@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Jim Lin <jilin@nvidia.com>
Subject: [PATCH 1/1] USB: EHCI: Tegra: Fix wrong register definition
Date: Tue, 18 Sep 2012 16:42:17 +0800 [thread overview]
Message-ID: <1347957737-14191-1-git-send-email-jilin@nvidia.com> (raw)
Fix the issue that EHCI registers, hostpc[0] and usbmode_ex,
are not correctly accessed on Tegra3 platform.
Signed-off-by: Jim Lin <jilin@nvidia.com>
---
include/linux/usb/ehci_def.h | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index de4b9ed..134bb4a 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -171,18 +171,18 @@ struct ehci_regs {
#define USBMODE_CM_HC (3<<0) /* host controller mode */
#define USBMODE_CM_IDLE (0<<0) /* idle state */
- u32 reserved4[7];
+ u32 reserved4[6];
/* Moorestown has some non-standard registers, partially due to the fact that
* its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
* PORTSCx
*/
/* HOSTPC: offset 0x84 */
- u32 hostpc[0]; /* HOSTPC extension */
+ u32 hostpc[1]; /* HOSTPC extension */
#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
#define HOSTPC_PSPD (3<<25) /* Port speed detection */
- u32 reserved5[17];
+ u32 reserved5[16];
/* USBMODE_EX: offset 0xc8 */
u32 usbmode_ex; /* USB Device mode extension */
--
1.7.3
next reply other threads:[~2012-09-18 8:38 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-18 8:42 Jim Lin [this message]
2012-09-18 14:33 ` Alan Stern
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