From: Youquan Song <youquan.song@intel.com>
To: linux-kernel@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
mingo@kernel.org, Stephane Eranian <eranian@google.com>,
"H. Peter Anvin" <hpa@linux.intel.com>,
Andi Kleen <andi@firstfloor.org>,
tglx@linutronix.de
Cc: Youquan Song <youquan.song@linux.intel.com>,
Youquan Song <youquan.song@intel.com>
Subject: [PATCH] x86,perf: Add IvyBridge EP support
Date: Tue, 18 Dec 2012 12:20:23 -0500 [thread overview]
Message-ID: <1355851223-27705-1-git-send-email-youquan.song@intel.com> (raw)
Run in perf utility at Ivybridge EP server, encouter "not supported" event
<not supported> L1-dcache-loads
<not supported> L1-dcache-load-misses
<not supported> L1-dcache-stores
<not supported> L1-dcache-store-misses
<not supported> L1-dcache-prefetches
<not supported> L1-dcache-prefetch-misses
This patch add the support for this processor.
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Youquan Song <youquan.song@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 324bb52..aea3503 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2075,6 +2075,7 @@ __init int intel_pmu_init(void)
pr_cont("SandyBridge events, ");
break;
case 58: /* IvyBridge */
+ case 62: /* IvyBridge EP */
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
--
1.6.4.2
next reply other threads:[~2012-12-18 5:14 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-18 17:20 Youquan Song [this message]
2013-01-05 14:12 ` Youquan Song
2013-01-24 20:30 ` [tip:perf/urgent] x86/perf: " tip-bot for Youquan Song
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