From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754625AbbJGOgr (ORCPT ); Wed, 7 Oct 2015 10:36:47 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:59504 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754504AbbJGOgo (ORCPT ); Wed, 7 Oct 2015 10:36:44 -0400 X-AuditID: cbfee68f-f796f6d0000014a4-fd-56152dfad056 Date: Wed, 07 Oct 2015 14:36:42 +0000 (GMT) From: Sarbojit Ganguly Subject: Re: Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange To: rmk+kernel@arm.linux.co.uk, Sarbojit Ganguly , "linux@arm.linux.org.uk" , "catalin.marinas@arm.com" Cc: Will Deacon , "Waiman.Long@hp.com" , "peterz@infradead.org" , VIKRAM MUPPARTHI , "linux-kernel@vger.kernel.org" , SUNEEL KUMAR SURIMANI , SHARAN ALLUR , "torvalds@linux-foundation.org" , "linux-arm-kernel@lists.infradead.org" Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20151007135155819@ganguly.s Msgkey: 20151007135155819@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20151007135155819@ganguly.s X-ParentMTR: X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <1357250509.710431444228599576.JavaMail.weblogic@epmlwas04a> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCIsWRmVeSWpSXmKPExsWyRsSkVveXrmiYQftCQ4vLu+awOTB6fN4k F8AYxWWTkpqTWZZapG+XwJWxccEM1oJvmhWztjxkb2B8odHFyMEhJKAi0TcpoouRk0NCwETi zZmnjBC2mMSFe+vZQGwhgaWMEidfFcDUbH6wkamLkQsoPodR4lLzahaQBAvQnJm3/4E1sAno S5ze/5IJxBYWiJQ4/u4pM0iDiMBeRomFpzvBupkFnjBLfO4/ywixQl6i/cV2sA5eAUGJkzOf sECsU5I4PfsQC0RcWWLi1x42iLicxJKpl5kgbF6JGe1PWWDi076uYYawpSXOz9oA987i74+h 4vwSx27vgOoVkJh65iBUjbrE62U/oeJ8EmsWvmWBqd91ajkzzK6Gjb/ZIWwJia0tT1hBbGYB RYkp3Q/ZIWwDiSOL5rCi+oUDyPaQaH5UDNE6lUPiaJf7BEalWUiqZiGZNAvJJGQ1CxhZVjGK phYkFxQnpRcZ6xUn5haX5qXrJefnbmIEJobT/57172C8e8D6EKMAB6MSD+8PY5EwIdbEsuLK 3EOMpsB4msgsJZqcD0w/eSXxhsZmRhamJqbGRuaWZkrivAulfgYLCaQnlqRmp6YWpBbFF5Xm pBYfYmTi4JRqYBSKPsVgeUG6b/OPQ91OMfxF2zz5MtlZtL8EHvqrmmWz+FpK3RTn509/GYbc K9j1oTA0R9noqXV816fFj1f33I51fxXNcXKfuax9gZRa2Mzdl78IJc499cZ+wqf+tXHsjzTa 1wa589XvClL0vh7yZfnBfz6sccFHtbdOX5ldO0lX66Nl1IeNVkosxRmJhlrMRcWJAMo5DhEH AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsVy+t/tPt1fuqJhBlNfa1lc3jWHzYHR4/Mm uQDGqDSbjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCh SgpliTmlQKGAxOJiJX07m6L80pJUhYz84hJbpWhDcyM9IwM9UyM9Q9NYK0MDAyNToJqEtIyN C2awFnzTrJi15SF7A+MLjS5GDg4hARWJvkkRXYycHBICJhKbH2xkgrDFJC7cW8/WxcgFVDKH UeJS82oWkAQLUP3M2//YQGw2AX2J0/tfgjUIC0RKHH/3lBmkQURgL6PEwtOdTCAOs8ATZonP /WcZQaqEBOQl2l9sB+vgFRCUODnzCQvEOiWJ07MPsUDElSUmfu1hg4jLSSyZehnqJF6JGe1P WWDi076uYYawpSXOz9rACHP24u+PoeL8Esdu74DqFZCYeuYgVI26xOtlP6HifBJrFr5lganf dWo5M8yuho2/2SFsCYmtLU9YQWxmAUWJKd0P2SFsA4kji+awovqFA8j2kGh+VDyBUXYWksws JN2zkHQjq1nAyLKKUTS1ILmgOCm9wkSvODG3uDQvXS85P3cTIzgRPVuyg7HhgvUhRgEORiUe 3h/GImFCrIllxZW5hxglOJiVRHgbvwOFeFMSK6tSi/Lji0pzUosPMZoCo20is5Rocj4wSeaV xBsam5ibGptaGBiam5spifPe3MsQJiSQnliSmp2aWpBaBNPHxMEp1cBoJLnxS+/Dna/fSh/M ZF/3TSt8y77vrAW79z50XvHeV0/8w7b0/ijTYO7UtQz7P87W2OpwnSMjrdkvTnPlnLzIDI03 BxaK/G6232vDc2jOy0ur6ufYzYndlzB/tu+epTVHmu7Oq/z0YI/QnWNVG8J6ndue+hy/dsxl p6lsStr0Q1bfJ0ZvMni1VomlOCPRUIu5qDgRAES97ZVaAwAA DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t97Earbm023245 Hello Russell, Please have a look at this patch, please let me know if any modification is required. I have also submitted the same in your patch system. v2 -> v3: Removed the comment related to Qspinlock, changed !defined to #ifndef. v1 -> v2: Extended the guard code to cover the byte exchange case as well following opinion of Will Deacon. Checkpatch has been run and issues were taken care of. Since support for half-word atomic exchange was not there and Qspinlock on ARM requires it, modified __xchg() to add support for that as well. ARMv6 and lower does not support ldrex{b,h} so, added a guard code to prevent build breaks. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 916a274..97882f9 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size switch (size) { #if __LINUX_ARM_ARCH__ >= 6 +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */ case 1: asm volatile("@ __xchg1\n" "1: ldrexb %0, [%3]\n" @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- 1.9.1 Regards, Sarbojit ------- Original Message ------- Sender : Will Deacon Date : Oct 06, 2015 20:24 (GMT+05:30) Title : Re: Re: Re: Re: [PATCH v3] arm: Adding support for atomic half word exchange On Tue, Oct 06, 2015 at 08:03:02AM +0000, Sarbojit Ganguly wrote: > Here is the version 3 of the patch correcting earlier issues. This looks good to me now: Acked-by: Will Deacon > v2 -> v3 : Removed the comment related to Qspinlock, changed !defined to > #ifndef. > v1 -> v2 : Extended the guard code to cover the byte exchange case as > well following opinion of Will Deacon. > Checkpatch has been run and issues were taken care of. The part of your text up until here doesn't belong in the commit message. You'll also need to send this to Russell's patch system. Will > Since support for half-word atomic exchange was not there and Qspinlock > on ARM requires it, modified __xchg() to add support for that as well. > ARMv6 and lower does not support ldrex{b,h} so, added a guard code > to prevent build breaks. > > Signed-off-by: Sarbojit Ganguly > --- > arch/arm/include/asm/cmpxchg.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h > index 916a274..c6436c1 100644 > --- a/arch/arm/include/asm/cmpxchg.h > +++ b/arch/arm/include/asm/cmpxchg.h > @@ -39,6 +39,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size > > switch (size) { > #if __LINUX_ARM_ARCH__ >= 6 > +#ifndef CONFIG_CPU_V6 /* MIN ARCH >= V6K */ > case 1: > asm volatile("@ __xchg1\n" > "1: ldrexb %0, [%3]\n" > @@ -49,6 +50,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size > : "r" (x), "r" (ptr) > : "memory", "cc"); > break; > + case 2: > + asm volatile("@ __xchg2\n" > + "1: ldrexh %0, [%3]\n" > + " strexh %1, %2, [%3]\n" > + " teq %1, #0\n" > + " bne 1b" > + : "=&r" (ret), "=&r" (tmp) > + : "r" (x), "r" (ptr) > + : "memory", "cc"); > + break; > +#endif > case 4: > asm volatile("@ __xchg4\n" > "1: ldrex %0, [%3]\n" > -- > 1.9.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I