From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756043Ab3AURye (ORCPT ); Mon, 21 Jan 2013 12:54:34 -0500 Received: from mail.free-electrons.com ([94.23.35.102]:54575 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754630Ab3AURya (ORCPT ); Mon, 21 Jan 2013 12:54:30 -0500 From: Gregory CLEMENT To: Jason Cooper , Andrew Lunn , Gregory Clement , Grant Likely , Rob Herring , John Stultz , Thomas Gleixner , Russell King Cc: Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Olof Johansson , Nicolas Pitre , Lior Amsalem , Maen Suleiman , Tawfik Bayouk , Shadi Ammouri , Eran Ben-Avi , Yehuda Yitschak , Nadav Haklai , Ike Pan , Jani Monoses , Chris Van Hoof , Dan Frazier , Leif Lindholm , Jon Masters , David Marlin , Sebastian Hesselbarth Subject: [PATCH 1/6] arm: mvebu: Add support for local interrupt Date: Mon, 21 Jan 2013 18:53:57 +0100 Message-Id: <1358790842-2986-2-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1358790842-2986-1-git-send-email-gregory.clement@free-electrons.com> References: <1358790842-2986-1-git-send-email-gregory.clement@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MPIC allows the use of private interrupt for each CPUs. The 28th first interrupts are per-cpu. This patch adds support to use them. Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mvebu/irq-armada-370-xp.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index f99a4a2..c007fdc 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -145,11 +145,19 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, { armada_370_xp_irq_mask(irq_get_irq_data(virq)); writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); - - irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, - handle_level_irq); irq_set_status_flags(virq, IRQ_LEVEL); - set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + + if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) { + + irq_set_percpu_devid(virq); + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_percpu_devid_irq); + + } else { + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_level_irq); + } + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); return 0; } @@ -245,7 +253,7 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs if (irqnr > 1022) break; - if (irqnr >= 8) { + if (irqnr > 0) { irqnr = irq_find_mapping(armada_370_xp_mpic_domain, irqnr); handle_IRQ(irqnr, regs); -- 1.7.9.5