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From: Yijing Wang <wangyijing@huawei.com>
To: Rob Landley <rob@landley.net>, Bjorn Helgaas <bhelgaas@google.com>
Cc: <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-pci@vger.kernel.org>,
	Andrew Murray <andrew.murray@arm.com>,
	Joe Lawrence <Joe.Lawrence@stratus.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	Hanjun Guo <guohanjun@huawei.com>, <jiang.liu@huawei.com>,
	Yijing Wang <wangyijing@huawei.com>
Subject: [PATCH v2] PCI: Document PCIE BUS MPS parameters
Date: Thu, 24 Jan 2013 10:58:08 +0800	[thread overview]
Message-ID: <1358996288-31200-1-git-send-email-wangyijing@huawei.com> (raw)

v0->v1: Update MPS parameters as non-arch and add MRRS
		description into pcie_bus_perf parameter suggested
		by Andrew Murray.
v1->v2: Update some semantic problems and add MPS and MRRS
		explanation suggested by Joe Lawrence and Randy Dunlap.

Document PCIE BUS MPS parameters pcie_bus_tune_off, pcie_bus_safe,
pcie_bus_peer2peer, pcie_bus_perf into Documentation/kernel-parameters.txt.
These parameters were introduced by Jon Mason <mason@myri.com> at
commit 5f39e6705 and commit b03e7495a8.

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
 Documentation/kernel-parameters.txt |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 363e348..0bb279f 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2227,6 +2227,22 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 				This sorting is done to get a device
 				order compatible with older (<= 2.4) kernels.
 		nobfsort	Don't sort PCI devices into breadth-first order.
+		pcie_bus_tune_off	Disable PCIe MPS (Max Payload Size)
+				turning and using the BIOS-configured MPS defaults.
+		pcie_bus_safe	Use the smallest common denominator MPS
+				of the entire tree below a root complex for every
+				device on that fabric. Can avoid inconsistent MPS
+				problem caused by hotplug.
+		pcie_bus_perf	Configure pcie device MPS to the largest
+				allowable MPS based on its parent bus. Also set
+				MRRS (Max Read Request Size) to the largest supported
+				value (no larger than the MPS that the device or bus
+				can support) for Max performance.
+		pcie_bus_peer2peer	Make the system-wide MPS the smallest
+				possible value (128B). This configuration could prevent
+				peer to peer DMA transmission from working by having
+				the MPS on one root port different than the MPS on
+				another.
 		cbiosize=nn[KMG]	The fixed amount of bus space which is
 				reserved for the CardBus bridge's IO window.
 				The default value is 256 bytes.
-- 
1.7.1



             reply	other threads:[~2013-01-24  2:58 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-01-24  2:58 Yijing Wang [this message]
2013-01-25  4:57 ` Bjorn Helgaas
2013-01-25  9:13   ` Yijing Wang

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