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Wed, 11 Nov 2026 06:41:08 -0800 (PST) Received: from [10.217.216.47] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b3b5b2fc09sm34141943c88.10.2026.11.11.06.41.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Nov 2026 06:41:08 -0800 (PST) Message-ID: <135bcaf6-f7f3-412b-9b13-494e6dd691e1@oss.qualcomm.com> Date: Wed, 11 Nov 2026 20:11:02 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] clk: qcom: segcc-nord: Add I2C and TSC clock support To: Taniya Das , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran Cc: Ajit Pandey , Imran Shaik , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20261107-gcc_i2c_tsc_support-v1-0-433d02972d7e@oss.qualcomm.com> <20261107-gcc_i2c_tsc_support-v1-2-433d02972d7e@oss.qualcomm.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: <20261107-gcc_i2c_tsc_support-v1-2-433d02972d7e@oss.qualcomm.com> Content-Type: text/plain; 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This permits consumers to enable > and reset the hardware through the common clock framework. > > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/segcc-nord.c | 187 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 187 insertions(+) > > diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c > index ef97da3852e3571db5c34676a8f08b9650d1e4c6..7fdfa44fb10360650e1bd59fc973f990788d3ed7 100644 > --- a/drivers/clk/qcom/segcc-nord.c > +++ b/drivers/clk/qcom/segcc-nord.c > @@ -29,6 +29,7 @@ enum { > P_BI_TCXO, > P_SE_GCC_GPLL0_OUT_EVEN, > P_SE_GCC_GPLL0_OUT_MAIN, > + P_SE_GCC_GPLL1_OUT_MAIN, > P_SE_GCC_GPLL2_OUT_MAIN, > P_SE_GCC_GPLL4_OUT_MAIN, > P_SE_GCC_GPLL5_OUT_MAIN, > @@ -74,6 +75,23 @@ static struct clk_alpha_pll_postdiv se_gcc_gpll0_out_even = { > }, > }; > > +static struct clk_alpha_pll se_gcc_gpll1 = { > + .offset = 0x1000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .enable_reg = 0x57010, > + .enable_mask = BIT(1), > + .hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_gpll1", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, > + }, > + }, > +}; > + > static struct clk_alpha_pll se_gcc_gpll2 = { > .offset = 0x2000, > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > @@ -189,6 +207,43 @@ static const struct clk_parent_data se_gcc_parent_data_4[] = { > { .index = DT_SLEEP_CLK }, > }; > > +static const struct freq_tbl ftbl_se_gcc_cnoc_i2c_slave_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + { } > +}; > + > +static struct clk_init_data se_gcc_cnoc_i2c_slave_clk_src_init = { > + .name = "se_gcc_cnoc_i2c_slave_clk_src", > + .parent_data = se_gcc_parent_data_2, > + .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_no_init_park_ops, > +}; > + > +static struct clk_rcg2 se_gcc_cnoc_i2c_slave_clk_src = { > + .cmd_rcgr = 0x13034, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = se_gcc_parent_map_2, > + .freq_tbl = ftbl_se_gcc_cnoc_i2c_slave_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &se_gcc_cnoc_i2c_slave_clk_src_init, > +}; > + Please drop the i2c RCGs as these RCGs only support 19.2MHz and are under boot access and not controlled from HLOS. Thanks, Jagadeesh > +static const struct parent_map se_gcc_parent_map_5[] = { > + { P_BI_TCXO, 0 }, > + { P_SE_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_SE_GCC_GPLL5_OUT_MAIN, 3 }, > + { P_SE_GCC_GPLL1_OUT_MAIN, 4 }, > +}; > + > +static const struct clk_parent_data se_gcc_parent_data_5[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &se_gcc_gpll0.clkr.hw }, > + { .hw = &se_gcc_gpll5.clkr.hw }, > + { .hw = &se_gcc_gpll1.clkr.hw }, > +}; > + > static const struct freq_tbl ftbl_se_gcc_eee_emac0_clk_src[] = { > F(66666667, P_SE_GCC_GPLL0_OUT_MAIN, 9, 0, 0), > F(100000000, P_SE_GCC_GPLL0_OUT_MAIN, 6, 0, 0), > @@ -380,6 +435,22 @@ static struct clk_rcg2 se_gcc_gp2_clk_src = { > }, > }; > > +static struct clk_rcg2 se_gcc_i2c_slave_xo_clk_src = { > + .cmd_rcgr = 0x2c00c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = se_gcc_parent_map_2, > + .freq_tbl = ftbl_se_gcc_emac0_phy_aux_clk_src, > + .hw_clk_ctrl = true, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_i2c_slave_xo_clk_src", > + .parent_data = se_gcc_parent_data_2, > + .num_parents = ARRAY_SIZE(se_gcc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_no_init_park_ops, > + }, > +}; > + > static const struct freq_tbl ftbl_se_gcc_qupv3_wrap0_s0_clk_src[] = { > F(7372800, P_SE_GCC_GPLL0_OUT_MAIN, 1, 192, 15625), > F(14745600, P_SE_GCC_GPLL0_OUT_MAIN, 1, 384, 15625), > @@ -670,6 +741,21 @@ static struct clk_rcg2 se_gcc_qupv3_wrap1_s6_clk_src = { > .clkr.hw.init = &se_gcc_qupv3_wrap1_s6_clk_src_init, > }; > > +static struct clk_rcg2 se_gcc_tscss_clk_src = { > + .cmd_rcgr = 0x2a010, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = se_gcc_parent_map_5, > + .freq_tbl = ftbl_se_gcc_emac0_ptp_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_tscss_clk_src", > + .parent_data = se_gcc_parent_data_5, > + .num_parents = ARRAY_SIZE(se_gcc_parent_data_5), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > static struct clk_branch se_gcc_eee_emac0_clk = { > .halt_reg = 0x240b4, > .halt_check = BRANCH_HALT, > @@ -1079,6 +1165,44 @@ static struct clk_branch se_gcc_gp2_clk = { > }, > }; > > +static struct clk_branch se_gcc_i2c_slave_ahb_clk = { > + .halt_reg = 0x2c008, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x2c008, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x2c008, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_i2c_slave_ahb_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &se_gcc_cnoc_i2c_slave_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch se_gcc_i2c_slave_xo_clk = { > + .halt_reg = 0x2c004, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2c004, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_i2c_slave_xo_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &se_gcc_i2c_slave_xo_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > static struct clk_branch se_gcc_mmu_2_tcu_vote_clk = { > .halt_reg = 0x57040, > .halt_check = BRANCH_HALT_VOTED, > @@ -1456,6 +1580,57 @@ static struct clk_branch se_gcc_qupv3_wrap1_s_ahb_clk = { > }, > }; > > +static struct clk_branch se_gcc_tscss_ahb_clk = { > + .halt_reg = 0x2a00c, > + .halt_check = BRANCH_HALT_VOTED, > + .hwcg_reg = 0x2a00c, > + .hwcg_bit = 1, > + .clkr = { > + .enable_reg = 0x2a00c, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_tscss_ahb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch se_gcc_tscss_cntr_clk = { > + .halt_reg = 0x2a008, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2a008, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_tscss_cntr_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &se_gcc_tscss_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch se_gcc_tscss_etu_clk = { > + .halt_reg = 0x2a004, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2a004, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "se_gcc_tscss_etu_clk", > + .parent_hws = (const struct clk_hw*[]) { > + &se_gcc_tscss_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct gdsc se_gcc_emac0_gdsc = { > .gdscr = 0x24004, > .en_rest_wait_val = 0x2, > @@ -1481,6 +1656,7 @@ static struct gdsc se_gcc_emac1_gdsc = { > }; > > static struct clk_regmap *se_gcc_nord_clocks[] = { > + [SE_GCC_CNOC_I2C_SLAVE_CLK_SRC] = &se_gcc_cnoc_i2c_slave_clk_src.clkr, > [SE_GCC_EEE_EMAC0_CLK] = &se_gcc_eee_emac0_clk.clkr, > [SE_GCC_EEE_EMAC0_CLK_SRC] = &se_gcc_eee_emac0_clk_src.clkr, > [SE_GCC_EEE_EMAC1_CLK] = &se_gcc_eee_emac1_clk.clkr, > @@ -1520,9 +1696,13 @@ static struct clk_regmap *se_gcc_nord_clocks[] = { > [SE_GCC_GP2_CLK_SRC] = &se_gcc_gp2_clk_src.clkr, > [SE_GCC_GPLL0] = &se_gcc_gpll0.clkr, > [SE_GCC_GPLL0_OUT_EVEN] = &se_gcc_gpll0_out_even.clkr, > + [SE_GCC_GPLL1] = &se_gcc_gpll1.clkr, > [SE_GCC_GPLL2] = &se_gcc_gpll2.clkr, > [SE_GCC_GPLL4] = &se_gcc_gpll4.clkr, > [SE_GCC_GPLL5] = &se_gcc_gpll5.clkr, > + [SE_GCC_I2C_SLAVE_AHB_CLK] = &se_gcc_i2c_slave_ahb_clk.clkr, > + [SE_GCC_I2C_SLAVE_XO_CLK] = &se_gcc_i2c_slave_xo_clk.clkr, > + [SE_GCC_I2C_SLAVE_XO_CLK_SRC] = &se_gcc_i2c_slave_xo_clk_src.clkr, > [SE_GCC_MMU_2_TCU_VOTE_CLK] = &se_gcc_mmu_2_tcu_vote_clk.clkr, > [SE_GCC_QUPV3_WRAP0_CORE_2X_CLK] = &se_gcc_qupv3_wrap0_core_2x_clk.clkr, > [SE_GCC_QUPV3_WRAP0_CORE_CLK] = &se_gcc_qupv3_wrap0_core_clk.clkr, > @@ -1560,6 +1740,10 @@ static struct clk_regmap *se_gcc_nord_clocks[] = { > [SE_GCC_QUPV3_WRAP1_S6_CLK] = &se_gcc_qupv3_wrap1_s6_clk.clkr, > [SE_GCC_QUPV3_WRAP1_S6_CLK_SRC] = &se_gcc_qupv3_wrap1_s6_clk_src.clkr, > [SE_GCC_QUPV3_WRAP1_S_AHB_CLK] = &se_gcc_qupv3_wrap1_s_ahb_clk.clkr, > + [SE_GCC_TSCSS_AHB_CLK] = &se_gcc_tscss_ahb_clk.clkr, > + [SE_GCC_TSCSS_CLK_SRC] = &se_gcc_tscss_clk_src.clkr, > + [SE_GCC_TSCSS_CNTR_CLK] = &se_gcc_tscss_cntr_clk.clkr, > + [SE_GCC_TSCSS_ETU_CLK] = &se_gcc_tscss_etu_clk.clkr, > }; > > static struct gdsc *se_gcc_nord_gdscs[] = { > @@ -1570,11 +1754,14 @@ static struct gdsc *se_gcc_nord_gdscs[] = { > static const struct qcom_reset_map se_gcc_nord_resets[] = { > [SE_GCC_EMAC0_BCR] = { 0x24000 }, > [SE_GCC_EMAC1_BCR] = { 0x25000 }, > + [SE_GCC_I2C_BCR] = { 0x2c000 }, > [SE_GCC_QUPV3_WRAPPER_0_BCR] = { 0x26000 }, > [SE_GCC_QUPV3_WRAPPER_1_BCR] = { 0x27000 }, > + [SE_GCC_TSCSS_BCR] = { 0x2a000 }, > }; > > static const struct clk_rcg_dfs_data se_gcc_nord_dfs_clocks[] = { > + DEFINE_RCG_DFS(se_gcc_cnoc_i2c_slave_clk_src), > DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s0_clk_src), > DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s1_clk_src), > DEFINE_RCG_DFS(se_gcc_qupv3_wrap0_s2_clk_src), >