From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757558Ab3BVPFF (ORCPT ); Fri, 22 Feb 2013 10:05:05 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:5742 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757454Ab3BVPFB (ORCPT ); Fri, 22 Feb 2013 10:05:01 -0500 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Fri, 22 Feb 2013 07:03:29 -0800 From: Peter De Schrijver To: Peter De Schrijver CC: , , Mike Turquette , Stephen Warren , Prashant Gaikwad , Subject: [REPOST PATCH 0/2] Table lookup for mux clock type Date: Fri, 22 Feb 2013 17:02:27 +0200 Message-ID: <1361545358-22721-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchset adds a table lookup feature to the mux clock type. This will be used by the forthcoming Tegra114 clock implementation. Also instead of a fixed field width, a mask is used. This is because Tegra114 has some muxes where the parent selector is spread over several bitfields. The second patch adapts the tegra periph clock implementation which uses struct clk_mux directly. -- Mike, This patch is a dependency for the Tegra114 CCF implementation. Could you review it and merge on a topic branch so Stephen can pull it in to verify the integration? Thanks, Peter. Peter De Schrijver (2): clk: add table lookup to mux clk: tegra: adapt tegra periph clk to mux table/mask drivers/clk/clk-mux.c | 51 ++++++++++++++++++++++++++++++++--------- drivers/clk/tegra/clk.h | 27 +++++++++++++++------ include/linux/clk-private.h | 3 +- include/linux/clk-provider.h | 9 ++++++- 4 files changed, 69 insertions(+), 21 deletions(-) -- 1.7.7.rc0.72.g4b5ea.dirty