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September 2026, 10:01:08 Mitteleurop=C3=A4ische Normalzeit= schrieb Igor Paunovic: > rocket_core_init() hands core->clks to devm_clk_bulk_get() without ever > setting the .id members. The rocket_core array is allocated with > devm_kcalloc() in rocket_device_init(), and rocket_probe() only fills in > .rdev, .dev and .index, so all four clk_bulk_data entries are requested > with a NULL con_id (unlike core->resets, whose ids are set a few lines > above). >=20 > clk_get(dev, NULL) ends up in of_clk_get_hw(np, 0, NULL), and > of_parse_clkspec() only consults "clock-names" when a name was passed, > so the index stays 0 for all four entries. Every entry therefore ends up > holding a handle to the *first* clock of the DT "clocks" property, i.e. > ACLK_NPUn. Nothing fails: probe succeeds and the driver believes it owns > four different clocks. >=20 > The consequence is that rocket_device_runtime_resume() prepares and > enables the AXI clock four times, while hclk, pclk and - most > importantly - the NPU compute clock ("npu", SCMI_CLK_NPU on RK3588) are > never prepared or enabled by this driver at all. The NPU still works > only because the Rockchip power-domain driver sets GENPD_FLAG_PM_CLK and > its attach_dev() callback walks the device node with of_clk_get() and > adds every clock to the pm_clk list, so genpd happens to keep the > remaining clocks running. The bug is therefore latent today, but it > means the driver holds no reference to the clock that actually feeds the > NPU, which stands in the way of any future frequency scaling > (OPP/devfreq) work. >=20 > Found on an Orange Pi 5 Plus (RK3588) by reading the live clock tree: > /sys/kernel/debug/clk/clk_summary shows four "fdab0000.npu" consumer > handles on aclk_npu0 (and likewise on aclk_npu1/aclk_npu2 for the other > two cores), while hclk_npu0, pclk_npu_root and scmi_clk_npu have no > "fdab0000.npu" consumer at all - their only consumers are the > "npu@fdab0000" handles created by the power-domain driver via > of_clk_get(). >=20 > Set the ids explicitly, in the order mandated by the binding > (Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml): > aclk, hclk, npu, pclk. After the change the driver holds one handle per > distinct clock and clk_bulk_prepare_enable() covers all four. >=20 > Note that this is a user-visible tightening for out-of-tree DTs: the > old NULL-id requests resolved by index and succeeded no matter what > "clock-names" contained, while the named requests fail probe with > -ENOENT when one of the four names is missing. That is the right > outcome for in-tree users - the binding requires exactly these four > clock-names and rk3588-base.dtsi carries them on all three cores - but > a DT that relied on the permissive lookup goes from silently running on > the wrong clock handles to not probing at all, so record the change > here where git log will find it. >=20 > Fixes: ed98261b4168 ("accel/rocket: Add a new driver for Rockchip's NPU") > Assisted-by: LLM sparse checkpatch > Signed-off-by: Igor Paunovic > Tested-by: Sidong Yang > Tested-by: Diederik de Haas # NanoPC-T6 LTS, N= anoPC-T6 Plus > Reviewed-by: Sebastian Reichel > Reviewed-by: Jiaxing Hu > --- > Same diff and the same message text (his copy re-wraps the lines) as > 01/14 of Jiaxing Hu's RK3576 series, which carries this patch as well; > whichever lands first, the other drops it. The trailers differ: Jiaxing > asked me to drop his Signed-off-by from my own posting of it, as he did > not pass this copy along, and Assisted-by is added because an LLM helped > with the checks on this v2. >=20 > drivers/accel/rocket/rocket_core.c | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/ro= cket_core.c > index b3b2fa9ba645a..5dd260bacbff6 100644 > --- a/drivers/accel/rocket/rocket_core.c > +++ b/drivers/accel/rocket/rocket_core.c > @@ -28,6 +28,10 @@ int rocket_core_init(struct rocket_core *core) > if (err) > return dev_err_probe(dev, err, "failed to get resets for core %d\n", c= ore->index); > =20 > + core->clks[0].id =3D "aclk"; > + core->clks[1].id =3D "hclk"; > + core->clks[2].id =3D "npu"; > + core->clks[3].id =3D "pclk"; additionally, while reading the followup patches, please introduce some constants for the indices. ROCKET_CLK_ACLK, ... or some other name. Because when you access them later by index, that makes things harder to read and follow (especially in the future) Heiko