From: Soren Brinkmann <soren.brinkmann@xilinx.com>
To: Rob Herring <rob.herring@calxeda.com>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Ian Campbell <ian.campbell@citrix.com>,
Russell King <linux@arm.linux.org.uk>,
Michal Simek <michal.simek@xilinx.com>
Cc: linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
Soren Brinkmann <soren.brinkmann@xilinx.com>
Subject: [PATCH] arm: zynq: dt: Set correct L2 ram latencies
Date: Wed, 31 Jul 2013 16:24:59 -0700 [thread overview]
Message-ID: <1375313099-8402-1-git-send-email-soren.brinkmann@xilinx.com> (raw)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
---
arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6f54a64..e32b92b 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -41,8 +41,8 @@
L2: cache-controller {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
- arm,data-latency = <2 3 2>;
- arm,tag-latency = <2 3 2>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
--
1.8.3.4
next reply other threads:[~2013-07-31 23:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-31 23:24 Soren Brinkmann [this message]
2013-08-02 11:37 ` Michal Simek
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