From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751837Ab3HTA2U (ORCPT ); Mon, 19 Aug 2013 20:28:20 -0400 Received: from co1ehsobe002.messaging.microsoft.com ([216.32.180.185]:4251 "EHLO co1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751385Ab3HTA2D (ORCPT ); Mon, 19 Aug 2013 20:28:03 -0400 X-Forefront-Antispam-Report: CIP:163.181.249.109;KIP:(null);UIP:(null);IPV:NLI;H:ausb3twp02.amd.com;RD:none;EFVD:NLI X-SpamScore: 12 X-BigFish: VPS12(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hz70kd2iz1de098h177df4h17326ah1de096h8275eh8275bh1de097h3284oa1495iz2dh839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h1155h) X-WSS-ID: 0MRSZYG-02-3RW-02 X-M-MSG: From: Aravind Gopalakrishnan To: , , , , , , , , , CC: Aravind Gopalakrishnan Subject: [PATCH 1/1] AMD64_EDAC: Fix incorrect wrap arounds due to left shift beyond 32 bits. Date: Mon, 19 Aug 2013 19:27:52 -0500 Message-ID: <1376958472-2150-2-git-send-email-Aravind.Gopalakrishnan@amd.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1376958472-2150-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1376958472-2150-1-git-send-email-Aravind.Gopalakrishnan@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-OriginatorOrg: amd.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Link to the bug report: http://marc.info/?l=linux-edac&m=137692201732220&w=2 dct_base and dct_limit obtain 32 bit register values when they read their respective pci config space registers. A left shift beyond 32 bits will cause them to wrap around. Similar case for chan_addr as can be seen from the bug report. In the patch, we rectify this by casting chan_addr to u64 and by comparing dct_base and dct_limit against (sys_addr >> 27) Tested on F15h, M30h with ECC turned on and works fine. Signed-off-by: Aravind Gopalakrishnan diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b86228c..eb4793e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1558,11 +1558,12 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, } /* Verify sys_addr is within DCT Range. */ - dct_base = (dct_sel_baseaddr(pvt) << 27); - dct_limit = (((dct_cont_limit_reg >> 11) & 0x1FFF) << 27) | 0x7FFFFFF; + dct_base = dct_sel_baseaddr(pvt); + dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF; if (!(dct_cont_base_reg & BIT(0)) && - !(dct_base <= sys_addr && dct_limit >= sys_addr)) + !(dct_base <= (sys_addr >> 27) && + dct_limit >= (sys_addr >> 27))) return -EINVAL; /* Verify number of dct's that participate in channel interleaving. */ @@ -1614,7 +1615,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range, amd64_read_pci_cfg(pvt->F1, DRAM_CONT_HIGH_OFF + (int) channel * 4, &tmp); - chan_addr += ((tmp >> 11) & 0xfff) << 27; + chan_addr += (u64) ((tmp >> 11) & 0xfff) << 27; } f15h_select_dct(pvt, channel); -- 1.7.10.4