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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
	Mike Turquette <mturquette@linaro.org>,
	Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v5 04/15] clk: tegra: Add TEGRA_PERIPH_NO_DIV flag
Date: Fri, 18 Oct 2013 16:25:08 +0300	[thread overview]
Message-ID: <1382102719-5531-5-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1382102719-5531-1-git-send-email-pdeschrijver@nvidia.com>

This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-periph.c |   11 ++++++++---
 drivers/clk/tegra/clk.h        |    1 +
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 5102d5e..b5feccc 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -173,12 +173,16 @@ const struct clk_ops tegra_clk_periph_nodiv_ops = {
 static struct clk *_tegra_clk_register_periph(const char *name,
 			const char **parent_names, int num_parents,
 			struct tegra_clk_periph *periph,
-			void __iomem *clk_base, u32 offset, bool div,
+			void __iomem *clk_base, u32 offset,
 			unsigned long flags)
 {
 	struct clk *clk;
 	struct clk_init_data init;
 	struct tegra_clk_periph_regs *bank;
+	bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
+
+	flags |= periph->gate.flags & TEGRA_PERIPH_NO_DIV ?
+			CLK_SET_RATE_PARENT : 0;
 
 	init.name = name;
 	init.ops = div ? &tegra_clk_periph_ops : &tegra_clk_periph_nodiv_ops;
@@ -216,7 +220,7 @@ struct clk *tegra_clk_register_periph(const char *name,
 		u32 offset, unsigned long flags)
 {
 	return _tegra_clk_register_periph(name, parent_names, num_parents,
-			periph, clk_base, offset, true, flags);
+			periph, clk_base, offset, flags);
 }
 
 struct clk *tegra_clk_register_periph_nodiv(const char *name,
@@ -224,6 +228,7 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
 		struct tegra_clk_periph *periph, void __iomem *clk_base,
 		u32 offset)
 {
+	periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
 	return _tegra_clk_register_periph(name, parent_names, num_parents,
-			periph, clk_base, offset, false, CLK_SET_RATE_PARENT);
+			periph, clk_base, offset, CLK_SET_RATE_PARENT);
 }
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 997357e..a826720 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -397,6 +397,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 #define TEGRA_PERIPH_ON_APB BIT(2)
 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
+#define TEGRA_PERIPH_NO_DIV BIT(4)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
-- 
1.7.7.rc0.72.g4b5ea.dirty


  parent reply	other threads:[~2013-10-18 13:28 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1382102719-5531-1-git-send-email-pdeschrijver@nvidia.com>
2013-10-18 13:25 ` [PATCH v5 01/15] ARM: tegra30: add missing CLK IDs Peter De Schrijver
2013-10-20 21:31   ` Stephen Warren
2013-10-21  8:39     ` Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 02/15] clk: tegra: simplify periph clock data Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 03/15] clk: tegra: common periph_clk_enb_refcnt and clks Peter De Schrijver
2013-10-18 13:25 ` Peter De Schrijver [this message]
2013-10-18 13:25 ` [PATCH v5 05/15] clk: tegra: move some PLLC and PLLXC init to clk-pll.c Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 06/15] clk: tegra: move fields to tegra_clk_pll_params Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 07/15] clk: tegra: add header for common tegra clock IDs Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 08/15] clk: tegra: add common infra for DT clocks Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 09/15] clk: tegra: add clkdev registration infra Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 10/15] clk: tegra: move audio clk to common file Peter De Schrijver
2013-10-18 23:30   ` Andrew Bresticker
2013-10-18 13:25 ` [PATCH v5 11/15] clk: tegra: move periph clocks " Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 12/15] clk: tegra: move PMC, fixed clocks to common files Peter De Schrijver
2013-10-19  0:01   ` Andrew Bresticker
2013-10-18 13:25 ` [PATCH v5 13/15] clk: tegra: introduce common gen4 super clock Peter De Schrijver
2013-10-19  0:16   ` Andrew Bresticker
2013-10-18 13:25 ` [PATCH v5 14/15] clk: tegra: move tegra30 to common infra Peter De Schrijver
2013-10-18 13:25 ` [PATCH v5 15/15] clk: tegra: move tegra20 " Peter De Schrijver

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