From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754510Ab3J3O6f (ORCPT ); Wed, 30 Oct 2013 10:58:35 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43230 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754381Ab3J3O6c (ORCPT ); Wed, 30 Oct 2013 10:58:32 -0400 From: Sricharan R To: , , , , , , , , , , , , , , , CC: Benoit Cousson Subject: [PATCH V2 5/7] ARM: DTS: DRA7: Add routable-irqs property for gic node Date: Wed, 30 Oct 2013 20:27:18 +0530 Message-ID: <1383145040-15852-6-git-send-email-r.sricharan@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383145040-15852-1-git-send-email-r.sricharan@ti.com> References: <1383145040-15852-1-git-send-email-r.sricharan@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There is a IRQ crossbar device in the soc, which maps the irq requests from the peripherals to the mpu interrupt controller's inputs. The gic provides the support for such IPs in the form of routable-irqs. So adding the property here to gic node. Cc: Benoit Cousson Cc: Santosh Shilimkar Cc: Rajendra Nayak Cc: Tony Lindgren Signed-off-by: Sricharan R --- arch/arm/boot/dts/dra7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index afb89f1..6a5404f 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -59,6 +59,7 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; + arm,routable-irqs = <160>; reg = <0x48211000 0x1000>, <0x48212000 0x1000>, <0x48214000 0x2000>, -- 1.7.9.5